clash-compiler

Bugfix release

• Changed:

  • The hardwired functions to unroll primitive definitions for 'zipWith', 'map', 'foldr', and 'init' have been changed to only unroll a single step, whereas they would previously unroll the whole definition in one step. This allows Clash to take advantage of the lazy nature of these functions, in turn speeding up compilation speeds significantly in some cases. Part of PR 1354.

• Added:

  • Support for GHC 8.10
  • Ability to load designs from precompiled modules (i.e., stored in a package database). See #1172
  • Support for '-main-is' when used with --vhdl, --verilog, or --systemverilog
  • A partial instance for NFDataX (Signal domain a)

• Fixed:

  • Clash's evaluator now inlines work free definitions, preventing situations where it would otherwise get stuck in an infinite loop
  • caseCon doesn't apply type-substitution correctly #1340
  • Clash generates illegal SystemVerilog slice #1313
  • Fix result type of head and tail Verilog blackboxes #1351
  • Certain recursive let-expressions in side a alternatives of a case-expression throw the Clash compiler into an infinite loop #1316
  • Fixes issue with one of Clash's transformations, inlineCleanup, introducing free variables #1337
  • Fails to propagate type information of existential type #1310
  • Certain case-expressions throw the Clash compiler into an infinite loop #1320
  • Added blackbox implementation for 'Clash.Sized.Vector.iterateI', hence making it usable as a register reset value #1240
  • iterate and iterateI can now be used in reset values #1240
  • Prim evaluation fails on undefined arguments #1297
  • Missing re-indexing in (Un)Signed fromSLV conversion #1292
  • VHDL: generate a type qualification inside ~TOBV, fixes #1360

Bug fix release

• Changed:

  • Treat Signed 0, Unsigned 0, Index 1, BitVector 0 as unit. In effect this means that 'minBound' and 'maxBound' return 0, whereas previously they might crash #1183
  • Infix use of deepseqX is now right-associative

• Added:

  • Add 'natToInteger', 'natToNatural', and 'natToNum'. Similar to 'snatTo*', but works solely on a type argument instead of an SNat.
  • Clash.Sized.Vector.unfoldr and Clash.Sized.Vector.unfoldrI to construct vectors from a seed value
  • Added NFDataX instances for Data.Monoid.{First,Last}

• Fixed:

  • The Verilog backend can now deal with non-contiguous ranges in custom bit-representations.
  • Synthesizing BitPack instances for type with phantom parameter fails #1242
  • Synthesis of fromBNat (toBNat d5) failed due to unsafeCoerce coercing from Any
  • Memory leak in register primitives #1256
  • Illegal VHDL slice when projecting nested SOP type #1254
  • Vivado VHDL code path (-fclash-hdlsyn Vivado) generates illegal VHDL #1264

As promised when releasing 1.0, we've tried our best to keep the API stable. We
think most designs will continue to compile with this new version, although special
care needs to be taken when using:

• ..inline blackboxes. Instead of taking a single HDL, inline primitives now
  take multiple. For example, InlinePrimitive VHDL ".." must now be written
  as InlinePrimitive [VHDL] "..".

• ..the Enum instance for BitVector, Index, Signed, or Unsigned, as
  they now respect their maxBound. See #1089.

On top of that, we've added a number of new features:

• makeTopEntity: Template Haskell function for generating TopEntity annotations. See the documentation on Haddock for more information.

• Clash.Explicit.SimIO: ((System)Verilog only) I/O actions that can be translated to HDL I/O. See the documentation on Haddock for more information.

• Clash.Class.AutoReg: A smart register that improves the chances of synthesis tools inferring clock-gated registers. See the documentation on Haddock for more information.

View all the changes in the CHANGELOG. Happy hacking!

Bug fix release

• Fixes issues:

  • #810: Verilog backend now correctly specifies type of BitVector 1
  • #811: Improve module load behavior in clashi
  • #439: Template Haskell splices and TopEntity annotations can now be used in clashi
  • #818: Fixed various mistakes in tutorial
  • #662: Clash will now constant specialize partially constant constructs
  • #700: Check work content of expression in cast before warning users. Should eliminate a lot of (superfluous) warnings about "specializing on non work-free cast"s.
  • #837: Blackboxes will now report clearer error messages if they're given unexpected arguments.

• Small fixes without issue reports:

  • Fix bug in rnfX defined for Down (814fd52)
  • Report blackbox name when encountering an error in 'setSym' (#858)

10 year anniversary release!

• 10x - 50x faster compile times
• New features:
  • API changes: check the migration guide at the end of Clash.Tutorial
  • All memory elements now have an (implicit) enable line; "Gated" clocks have
    been removed as the clock wasn't actually gated, but implemented as an
    enable line.
  • Circuit domains are now configurable in:

    • (old) The clock period

    • (new) Clock edge on which memory elements latch their inputs
      (rising edge or falling edge)

    • (new) Whether the reset port of a memory element is level sensitive
      (asynchronous reset) or edge sensitive (synchronous reset)

    • (new) Whether the reset port of a memory element is active-high or
      active-low (negated reset)

    • (new) Whether memory element power on in a configurable/defined state
      (common on FPGAs) or in an undefined state (ASICs)

    • See the blog post on this new feature

  • Data types can now be given custom bit-representations: http://hackage.haskell.org/package/clash-prelude/docs/Clash-Annotations-BitRepresentation.html
  • Annotate expressions with attributes that persist in the generated HDL,
    e.g. synthesis directives: http://hackage.haskell.org/package/clash-prelude/docs/Clash-Annotations-SynthesisAttributes.html
  • Control (System)Verilog module instance, and VHDL entity instantiation names
    in generated code: http://hackage.haskell.org/package/clash-prelude/docs/Clash-Magic.html
  • Much improved infrastructure for handling of unknown values: defined spine,
    but unknown leafs: http://hackage.haskell.org/package/clash-prelude/docs/Clash-XException.html#t:NFDataX
  • Experimental: Multiple hidden clocks. Can be enabled by compiling
    clash-prelude with -fmultiple-hidden
  • Experimental: Limited GADT support (pattern matching on vectors, or custom
    GADTs as longs as their usage can be statically removed; no support of
    recursive GADTs)
  • Experimental: Use regular Haskell functions to generate HDL black boxes for
    primitives (in an addition to existing string templates for HDL black boxes)
    See for example: http://hackage.haskell.org/package/clash-lib/docs/Clash-Primitives-Intel-ClockGen.html

• New features:
  • Sum-of-product types: unused bits now "don't-care" #212
• Fixes bugs:
  • Eagerness bug in regEn #104 (Thanks to @cbiffle)

• New features:
  • Support distribution of primitive templates with Cabal/Hackage packages commit
  • Find memory data files and primitive files relative to import dirs (-i<DIR>)
  • Add 'clashi' program and 'clash-ghc' package #208, thanks to @thoughtpolice
• Fixes bugs:
  • case (EmptyCase ty) of ty' { ... } -> EmptyCase ty' #198
  • BitVector.split# apply the correct type arguments
  • SystemVerilog: Incorrect unsigned->signed wrap-around and conversion
  • SystemVerilog: Use unpacked array syntax in array literals
  • SystemVerilog: Add braces when converting unpacked to packed arrays
  • SystemVerilog: Fixed rotateLeftS systemverilog template
  • SystemVerilog: Do not generate null-slices
  • Verilog: Incorrect unsigned->signed wrap-around and conversion
  • VHDL: resize Integer multiplication result

• New features:
  • CLaSH.XException: a module defining an exception representing uninitialised values. Additionally adds the ShowX class which has methods that prints values as "X" where they would normally raise an XException exception.
  • Add BNat (and supporting functions) to CLaSH.Promoted.Nat: base-2 encoded natural numbers.
  • Add divSNat and logBaseSNat to CLaSH.Promoted.Nat: division and logarithm for singleton natural numbers.
  • Add predUNat and subUNat to CLaSH.Promoted.Nat: predecessor and subtraction for unary-encoded natural numbers.
  • Add dtfold to CLaSH.Sized.Vector: a dependently-typed tree-fold over Vec.
  • Add the perfect-depth binary trees module CLaSH.Sized.RTree
  • Synthesisable definitions of countLeadingZeros and countTrailingZeros for: BitVector, Signed, Unsigned, and Fixed
  • Add the (:::) type alias in CLaSH.NamedTypes which allows you to annotate types with documentation
• Changes:
  • asyncRam, blockRam, blockRamFile have a Maybe (addr,a) as write input instead of three separate Bool, addr, and a inputs.
  • asyncFIFOSynchronizer has a Maybe a as write-request instead of a separate Bool and a input
  • bundle' and unbundle' are removed; bundle now has type Unbundled' clk a -> Signal' clk a, unbundle now has type Signal' clk a -> Unbundled' clk a
  • subSNat now has the type SNat (a+b) -> SNat b -> SNat a (where it used to be SNat a -> SNat b -> SNat (a-b))
  • Renamed multUNat to mulUNat to be in sync with mulSNat and mulBNat.
  • The function argument of vfold in CLaSH.Sized.Vector is now (forall l . SNat l -> a -> Vec l b -> Vec (l + 1) b) (where it used to be (forall l . a -> Vec l b -> Vec (l + 1) b))
  • Cons constructor of Vec is no longer visible; (:>) and (:<) are now listed as constructors of Vec
  • Simulation speed improvements for numeric types

• Call generatePrimMap after loadModules #175
• Fixes bugs:
  • (System)Verilog: CLaSH.Sized.Vector.imap primitive gets indices in reverse order
  • Template Haskell splices are run twice
  • CLaSH errors out when observing the constructor for Signal #174

• Fixes bugs:
  • Bug in DEC transformation overwrites case-alternatives
  • Bug in DEC transformation creates non-representable let-binders
  • VHDL: Incorrect primitive for Integers ltInteger# and geInteger#
  • (System)Verilog: Fix primitive for CLaSH.Sized.Internal.Signed.mod# and GHC.Type.Integer.modInteger #164

• New features:
  • Better error location reporting
• Fixes bugs:
  • CLaSH.Sized.Internal.Unsigned.maxBound# not evaluated at compile-time #155
  • CLaSH.Sized.Internal.Unsigned.minBound# not evaluated at compile-time #157
  • Values of type Index 'n', where 'n' > 2^MACHINE_WIDTH, incorrectly considered non-synthesisable due to overflow
  • VHDL: Types in generated types.vhdl incorrectly sorted
  • Casts of CLaSH numeric types result in incorrect VHDL/Verilog (Such casts are now reported as an error)

• Fixes bugs:
  • Eq instance of Vec sometimes not synthesisable
  • VHDL: Converting product types to std_logic_vector fails when the clash-hdlsyn Vivado flag is enabled

• New features:
  • DEC transformation also lifts HO-primitives applied to "interesting" primitives (i.e. zipWith (*))
  • New -clash-hdlsyn Xilinx flag to generate HDL tweaked for Xilinx synthesis tools (both ISE and Vivado)
• Fixes bugs:
  • replicate unfolded incorrectly #150
  • imap is not unrolled #151
  • VHDL: Incorrect primitive specification for snatToInteger #149

• New features:
  • Up to 2x reduced compilation times when working with large Vec literals
• Fixes bugs:
  • VHDL: Incorrect primitives for BitVectors quot# and rem#
  • VHDL: Bit indexing and replacement primitives fail to synthesise in Synopsis tools
  • Bug in DEC transformation throws CLaSH into an endless loop #140
  • Missed constant folding opportunity results in an error [#50](https://github.com/clash-lang/clash-

• New features:
  • Also generate testbench for circuits without input ports #135
• Fixes bugs:
  • clockWizard broken #49

0.6.15 March 15th 2016

• Fixes bugs:
  • XST cannot finds "_types" package unless it is prefixed with "work." #133

• Fixes bugs:
  • XST cannot finds "_types" package unless it is prefixed with "work." #133

• Fixes bugs:
  • Not all lambda's in a function position removed

• Fixes bugs:
  • Not all lambda's in a function position removed due to bad eta-expansion #132

• New features:
  • Add support for HDL synthesis tool specific HDL generation:
    • New -clash-hdlsyn Vivado flag to generate HDL tweaked for Xilinx Vivado
  • Preserve more Haskell names in generated HDL #128
• Fixes bugs:
  • VHDL: Vivado fails to infer block ram #127
    • Users must use the -clash-hdlsyn Vivado flag in order to generate Xilinx Vivado specific HDL for which Vivado can infer block RAM.