• New features:
  • hdl files can be written to a directory (set by the -clash-hdldir flag) other than the current working directory #125.
    Also respects the -outputdir directory, unless:
    • -clash-hdldir is set to a different directory.
    • -hidir, -stubdir, and -dumbdir are not the same directory as -odir
• Fixes bugs:
  • caseCon transformation does not work on non-exhaustive case-expressions #123
  • VHDL: insufficient type-qualifiers for concatenation operator #121
  • Primitive reductions don't look through Signal #126

• New features:
  • Support for Debug.Trace.trace, thanks to @ggreif
• Fixes bugs:
  • case undefined of ... should reduce to undefined #116
  • VHDL/SystemVerilog: BlockRAM elements must be bit vectors #113
  • Type families obscure eligibility for synthesis #114

• New features:
  • Support for Haskell's: Char, Int8, Int16, Int32, Int64, Word, Word8, Word16, Word32, Word64.
  • Int/Word/Integer bitwidth for generated HDL is configurable using the -clash-intwidth=N flag, where N can be either 32 or 64.
• Fixes bugs:
  • Cannot reduce case error ... of ... to error ... #109

• Support for unbound-generics-0.3
• New features:
  • Only look for 'topEntity' in the root module. #22
• Fixes bugs:
  • Unhelpful error message when GHC is not in PATH #104

• New features:
  • Remove all existing HDL files before generating new ones. This can be disabled by the -clash-noclean flag. #96
  • Support for clash-prelude 0.10.4

• Fixes bugs:
  • Integer literals used as arguments not always properly annotated with their type.
  • Verilog: Name collision in verilog code #93
  • (System)Verilog: Integer literals missing "32'sd" prefix when used in assignments.
  • VHDL: Integer literals should only be capped to 32-bit when used in assignments.
  • Verilog: HO-primitives incorrect for nested vectors.

• Fixes bugs:
  • Reversing alternatives is not meaning preserving for literal patterns #91
  • DEC: root of the case-tree must contain at least 2 alternatives #92
  • Do not generate overlapping literal patterns in VHDL #91

• New features:
  • Improve DEC transformation: consider alternatives before the subject when checking for disjoint expressions.
• Fixes bugs:
  • DEC: don't generate single-branch case-expressions #90

• New features:
  • Support clash-prelude 0.10.2
• Fixes bugs:
  • CLaSH interpreter was reading '.ghci' file instead of '.clashi' file #87
  • DEC: Subject and alternatives are not disjoint #88

• New features:

  • Support for clash-prelude 0.10.1

  • Transformation that lifts applications of the same function out of alternatives of case-statements. e.g.

    case x of
      A -> f 3 y
      B -> f x x
      C -> h x
    

    is transformed into:

    let f_arg0 = case x of {A -> 3; B -> x}
        f_arg1 = case x of {A -> y; B -> x}
        f_out  = f f_arg0 f_arg1
    in  case x of
          A -> f_out
          B -> f_out
          C -> h x
    

• Fixes bugs:
  • clash won't run when not compiled with usual ghc #82
  • Fail to generate VHDL with blockRamFile' in clash-ghc 0.6 #85
  • Case-statements acting like normal decoder circuits are erroneously synthesised to priority decoder circuits.

• New features:
  • Support clash-prelude-0.10
  • Pattern matching on CLaSH.Sized.Vector's :> is now supported
  • Unroll "definitions" of the following primitives: fold, dfold, foldr

• New features:
  • Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
• Fixes bugs:
  • --systemverilog switch incorrectly generates verilog code instead of systemverilog code
  • Incorrect SV primitive for CLaSH.Prelude.Testbench.assert'
  • Incorrect SV primitive for CLaSH.Sized.Vec.index_int
  • Sometimes created incorrect nested generate statements in SV backend

• New features:
  • Support for copying string literals from Haskell to generated code
  • Support clash-prelude-0.9
  • Size at below which functions are always inlined is configurable, run with -clash-inline-below=N to set the size limit to N
  • Collect and copy data-files
• Fixes bugs:
  • Signals declared twice when not using a clock-generating component #60
  • This piece of code eat up all CPU when generating verilog #62
  • Can not operate "shiftR" on Int #63
  • Fail to generate verilog when using "quot" and "div" on Index #64

• Fixes bugs:
  • Treat BlackBox expressions as declarations when DC args. #37
  • Don't inline recursive closed bindings

• New features:
  • Support for clash-prelude 0.6
• Fixes bugs:
  • Ambiguous type: 'std_logic_vector' or 'std_ulogic_vector' #33
  • clash-ghc ignores "-package-db" flag #35

• Fixes bugs:
  • Compile with GHC 7.8.3 #31

clash-lib

• Fixes bugs:
  • VHDL array constant ambiguous #18
  • Exception: can't create selector #24
  • Calls to vhdlTypeMark don't result to inclusion of VHDL type in types.vhdl #28

clash-ghc

• Fixes bugs:
  • Type synonym improperly expanded #17
  • BlackBox for Signed maxBound and minBound generate incorrect VHDL. #19
  • Generate failure code in the VHDL for recSelError #23