The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
OTHER License
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Published by ASintzoff 7 months ago
This is the first release of a new series.
Too many changes since previous release to be reported here.
Full Changelog: https://github.com/openhwgroup/cva6/compare/v4.2.0...v5.0.0
Published by msfschaffner over 5 years ago
a0
and a1
registers via the bootromwt_axi_adapter
(only appeared when dcache lines were wider than icache lines)axi_lite_interface
load_store_unit
fpnew
to v0.5.5
axi
to v0.7.0
common_cells
to v1.13.1
riscv-dbg
to v0.1
axilite
to PLIC shim for OpenPiton+Arianein
and out
aliases for AXI interfacessd
flag in mstatus
Vivado 2018.3
4.014
Published by zarubaf over 5 years ago
riscv-isa-sim
tandem simulationPublished by zarubaf almost 6 years ago
aw_top
signal for close to memory atomicscore_id
/ cluster_id
inputs have been merged to hard_id input (interface changes)