netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

OTHER License

Stars
105
View Code on GitHub
Ecosystems: C

Statistics for this project are still being loaded, please check back later.

Related Projects
SimpleScalar

Modified version of SimpleScalar (3.0e) for store memory access trace.

31 Aug 2014 7
picotcp

PicoTCP is a free TCP/IP stack implementation

20 Feb 2013 1,176
XCircuit

XCircuit circuit drawing and schematic capture tool

26 Mar 2019 103
litex

Build your hardware, easily!

07 Nov 2015 2,687
openmodelica-javascript

Code to compile OpenModelica models to JavaScript

21 Sep 2013 62
qrouter

Qrouter detail router for digital ASIC designs

26 Mar 2019 55
simavr

simavr is a lean, mean and hackable AVR simulator for linux & OSX

14 May 2012 1,567
tinytapeout_mcpu5

8 bit CPU optimized for the constraints of tinytapeout

31 Aug 2022 8
irsim

IRSIM switch-level simulator for digital circuits

26 Mar 2019 31