Verilog ADPCM decoder compatible with OKI MSM5205
GPL-3.0 License
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JT5205 is an ADPCM sound source written in Verilog, fully compatible with OKI MSM5205.
If you are using JT5205 in a git project, the best way to add it to your project is:
git submodule add https://github.com/jotego/jt5205.git
The advantages of a using a git submodule are:
Name | Direction | Width | Purpose |
---|---|---|---|
rst | input | active-high asynchronous reset signal | |
clk | input | clock | |
cen | input | clock enable. | |
sel | input | 2 | selects the data rate |
din | input | 4 | input data |
sound | output | 12 | signed sound output |
This is a pin-to-pin compatible module with OKI MSM5205. If you are just going to use it on a retro core you don't need to know the internals of it just hook it up and be sure that the effective clock rate, i.e. clk&cen signal, is the intended 384kHz (or whatever your system needs).
If you hear a periodic noise when there should be no output, check whether your target system was leaving the MSM5205 halted at reset when no output was needed. If The part is not reset it will keep processing the output and a constant 0 input will produce a repetitive noise.
The VCLK output is by default a 1-clock cycle strobe suitable as a clock enable signal. To get a 50% duty cycle on it, instantiate the cell with the parameter VCLK_CEN set to zero.
Other sound chips from the same author
Chip | Repository |
---|---|
YM2203, YM2612, YM2610 | JT12 |
YM2151 | JT51 |
YM3526 | JTOPL |
YM2149 | JT49 |
sn76489an | JT89 |
OKI 6295 | JT6295 |
OKI MSM5205 | JT5205 |