Experimental flows using nextpnr for Xilinx devices
ISC License
nextpnr is a open-source multi-architecture place-and-route framework aimed at real-world FPGA silicon. This is an experiment to integrate nextpnr with RapidWright, an open interface into Xilinx FPGAs, and Project Xray, open bitstream documentation for xc7 FPGAs.
Currently two flows are supported:
$RAPIDWRIGHT_PATH
is set correctly for all further stepsgit submodule init
and git submodule update
to fetch the database and metadataA brief (academic) paper describing the Yosys+nextpnr flow can be found on arXiv.
cmake -DARCH=xilinx .
make
(with -jN as appropriate)cmake -DARCH=xilinx -DRAPIDWRIGHT_PATH=/path/to/rapidwright -DGSON_PATH=/path/to/gson-2.8.5.jar .
make
(with -jN as appropriate)pypy3 xilinx/python/bbaexport.py --device xc7a35tcsg324-1 --bba xilinx/xc7a35t.bba
(regular cpython works as well, but is a lot slower)./bba/bbasm --l xilinx/xc7a35t.bba xilinx/xc7a35t.bin
XRAY_DIR
to the path where Project Xray has been cloned and built (you may also need to patch out the Vivado check for utils/environment.sh
in Xray by removing this line and everything beyond it: https://github.com/SymbiFlow/prjxray/blob/80726cb73ba5c156549d98a2055f1ee3eff94530/utils/environment.sh#L52)attosoc.sh
in xilinx/examples/arty-a35
.java -jar rapidwright_bbaexport.jar xczu7ev-ffvc1156-2-e xilinx/constids.inc xilinx/xczu7ev.bba
./bba/bbasm --l xilinx/xczu7ev.bba xilinx/xczu7ev.bin
blinky.sh
in xilinx/examples/zcu104
.Run java -jar rapidwright_bbaexport.jar xczu2cg-sbva484-1-e xilinx/constids.inc xilinx/xczu2cg.bba
xczu2cg-sbva484-1-e
and the bba filename with the device you want to target. You can build multipleRun ./bba/bbasm --l xilinx/xczu2cg.bba xilinx/xczu2cg.bin
See xilinx/examples for example scripts that run the Yosys/nextpnr/RapidWright flow, then use Vivado to write a Verilog simulation netlist.
Currently supported:
xc7 and xcup: LUTs (including fractured), FFs, DRAM (only RAM64X1D), carry (XORCY and MUXCY or CARRY4), SRL16E and SRLC32E (no cascading), BRAM and IO
xcup: OSERDESE3, ISERDESE3, IDDRE1, ODDRE1, IDELAYE3, ODELAYE3, IDELAYCTRL, BUFGCTRL, BUFG, BUFGCE, BUFG_PS, PLLE4_ADV, PLLE4_BASIC, MMCME4_ADV, MMCME4_BASIC, URAM288E, DSP48E2 (no cascading)
xc7: OSERDESE2, ISERDESE2, IDDR, ODDR, IDELAYE2, ODELAYE2, IDELAYCTRL, BUFGCTRL, BUFG, PLLE2_BASIC, PLLE2_ADV, DSP48E1 (cascading works)
Bels, tile wires and pips are deduplicated but nodes (connections between tile wires) are not. This means that databases for larger devices will be several gigabytes in size (but significantly smaller than a fully flat database).