fusesoc

• Add CLI to read/write config settings
• Separate CLI from library to ease integration
• Add --work-root to directly set output dir
• Show core filename with "fusesoc core show"
• Allow matching against only "name" component in VLNV
• Improve inheritance rules between targets
• Warn on duplicate cores
• Support prepend keyword for generators
• Reenable Windows tests
• + improved error handling, bug fixes and refactoring

Bugfix release

• Use jsonschema to describe and validate CAPI2 files
• Add switch to allow additional CAPI2 properties
• Support use expansion everywhere
• Support setting tags on files
• • improved error handling, bug fixes and refactoring

• Add caching of generators
• Allow setting library version when adding libraries
• Allow cloning repos that don't support shallow clones
• Avoid cleaning out existing work roots
• Only re-export changed files
• • improved error handling, bug fixes and refactoring

• Better usability as a module
• Require Python 3.6
• git provider : Use shallow clones
• Remove CAPI1 support
• Improved documentation
• Support Integer type in tool options
• Run generators in unique temp directories
• Support copying directories with copyto
• Support setting flags in targets
• Remove fusesoc pgm, update and init commands
• Support virtual packages in CAPI2
• Add config file option to ignore directories
• Add CLI command to list Edalize backends
• Add support for Edalize flow API
• Put source in work_root subdirectory in the build tree
• Avoid endless symlink recursion
• Enable use flags in tool options
• Add CLI flag to evaluate env vars in core files
• Remove deprecated cores_root and systems_root config file options
• Remove deprecated logicore and coregen providers

This release is available for installation from PyPi through pip.

See https://olofkindgren.blogspot.com/2021/02/fusesoc-112.html for the release announcement.

Changes:

• fusesoc pgm and init are deprecated
• Deprecated build and sim commands are removed
• logicore and coregen providers are deprecated
• Instance parameters can be set from target
• Rewritten documentation
• • improved error handling, bug fixes and refactoring

This release is available for installation from PyPi through pip.

Note that this is the first release supporting only Python 3.5+. Use fusesoc <= 1.10 if you need to use Python 2.

Changes:

• Remove python 2 support

• Improved CI checks

• Add CAPI2 support for setting include_path

• Relicensed to 2-clause BSD license

• Allow using parameters defined in dependencies

• Support real (float) parameters

• • improved error handling, bug fixes and refactoring

This release is available for installation from PyPi through pip.

Note that FuseSoC 1.10 is the last release to support Python 2.7, all following releases will be Python 3.5+ only!

• Add generators support

• Split out edalize to a separate package

• CAPI1 support for Trellis backend

• CAPI1 support for VCS backend

• • improved error handling, bug fixes and refactoring

Contributors:
Anonymous
David Shah [email protected]
Jonathan Balkind [email protected]
Olof Kindgren [email protected]
Philipp Wagner [email protected]

• Improve plusargs handling
• Fix core-info for verilator sections
• Allow multiple top-level modules in Icarus
• Fix VHDL and SystemVerilog support in ISIM
• Add support for the GHDL simulator
• Add support for Vivado Logicore cores
• Add support for ISE CoreGen cores
• Support IP-XACT 2009 and 2014 versions
• Add icestorm backend
• Allow settings default values for parameters
• Add support for Altera qip files
• Add CI testing with Travis and appveyor
• Experimental Windows support
• Allow Modelsim to run user TCL files
• Parallelize verilator jobs to speed up compilation
• + improved error handling, bug fixes and refactoring

• Allow setting top-level parameters in backends
• Allow FuseSoC to handle verilator CLI arguments
• Parse command-line before building sim model
• Support plusargs in XSIM
• Initial IP-Xact support (FileSets and description)
• Add distutils-based build system and add to pypi
• Support mixed-language (VHDL, verilog, SV) in ModelSim
• Support mixed-language (VHDL, verilog, SV) in XSIM
• Add fileset sections (replaces vhdl/verilog sections)
• Allow per-file attributes in .core
• + improved error handlig, bug fixes and refactoring

• Add item to .core files to explicitly apply patches
• Export FuseSoC dirs as env vars to external commands
• Use relative paths everywhere
• Always rebuild sim model, except when --keep is used
• Prettify core-info output
• Generate CAPI directly from section.py
• Add more helpful data types to section members
• Support multiple top-level testbenches
• Add git provider
• Add pgm option to ISE backend
• Add support for Xilinx ISIM Simulator
• Abort FuseSoC on scripts with non-zero return code
• Run scripts from all core deps in simulations
• Add parameter section (replaces plusargs)
• Add support for Xilinx XSIM Simulator
• + improved error handling, bug fixes and refactoring