Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
MIT License
This library contains universal HDL AST nodes (Hardware Description Language Abstract Syntax Tree = objects for representation of code constructs) for SystemVerilog, VHDL and others. This AST can be generated from SV/VHDL code by hdlConvertor and it can also be converted to VHDL/SV/JSON/SystemC/... and other formats using hdlConvertorAst.to module. Note that the conversion of AST of different languages requires an extra care. E. g. the VHDL AST and SV AST will have a different type names and thus the direct transpilation using hdlConvertorAst.to module will not yield working code. If source and target language differs the translation is required. For this translations and post processing you can use hdlConvertorAst.translate module
Doc shared with hdlConvertor.
tool_directive
and PSL
)# note this may be older version than you see in repo
sudo pip3 install hdlConvertorAst
# or download repository and run
sudo python3 setup.py install
# if you are using version from git rather uninstall
# old library first if required
# sudo pip3 uninstall hdlConvertorAst