A microcontroller that natively executes a simple LISP dialect
APACHE-2.0 License
This is a simple microcontroller that runs a compiled LISP dialect. Details of operation are in the wiki.
This uses Icarus Verilog for simulation (http://iverilog.icarus.com/). Tests are located in the tests/ directory. Run them as follows:
make test
The test runner searches files for patterns that begin with 'CHECK:'. The output of the program will be compared to whatever comes after this declaration. If they do not match, an error will be flagged.
Compile the LISP sources. This produces two files: program.hex, which has the raw program machine code and is loaded by the simulator, and program.lst, which is informational and shows details of the generated code. For example:
./compile.py tests/test1.lisp
Note that any writes to register index 0 will be printed to standard out by the simulation test harness, which is how most simulation tests work.
Run simulation. The simulator will read rom.hex each time it starts.
vvp sim.vvp
This has only been tested under Quartus/Altera with the Cyclone II starter kit. There are a couple of projects located under the fpga/ directory:
Compile the LISP sources. These are located in the project directory, but must be compiled from the top directory. For example, from LispMicrocontroller/
./compile.py fpga/game/game.lisp
rom.hex will be created in the top level LispMicrocontroller/ directory.
Synthesize the design Open the program file (for example, fpga/game/game.qpf). Note that the synthesis tools will read rom.hex to create the values for program ROM. If you recompile the LISP sources (thereby changing rom.hex), the design must be re-synthesized.
Run using the programmer included with Quartus.