Yet Another AES implementation in hardware.
LGPL-3.0 License
VHDL implementation of the symmetric block cipher AES, as specified in the NIST FIPS 197, respectively NIST SP 800-38A.
Features:
Mode | Encryption | Decryption |
---|---|---|
ECB | ✔️ | ❌ |
CBC | ✔️ | ❌ |
CFB | ✔️ | ✔️ |
OFB | ✔️ | ✔️ |
CTR | ❌ | ❌ |
Development status:
The core expects key, iv (optional) and plaintext/ciphertext (depending if encrypting or decrypting) through islv_data
. A new set of key and iv should be signalised by assigning isl_new_key_iv
for one cycle. Valid inputs should be marked by assigning the isl_valid
signal. Accordingly, the output oslv_data
is valid when the signal osl_valid
is assigned. New input data can be transmitted only when the output is fully done.
Example for AES-256 encryption in CFB mode with an interface bitwidth of 32 bit:
The following results are obtained from a local synthesis for Lattice ECP5, using the open source toolchain (ghdl, yosys and nextpnr). For more details, see the synthesis workflow.
From the testsuite runs, the following metrics can be derived (configuration as above):