RISC-V 32bit CPU written in Chisel. This project is for my learning purpose to understand how to design/implement hardware with Chisel and what RISC-V architecture is. Working in progress.
rvv-0.9.x
branch but it should refer to rvv-intrinsic
branch for RVV v1.0-rc.This repository was imported from chisel-template@f5f33c6.
Clone this repository:
git clone --recursive https://github.com/rhysd/riscv32-cpu-chisel.git
Build Docker image for RISC-V GNU toolchain and Scala toolchain:
docker build . -t riscv/mycpu
Start an interactive shell with mounting this repository:
docker run -it -v $(pwd):/app riscv/mycpu
Verilog sources can be generated from Chisel sources via sbt run
:
make ./c/fib.hex # Make hex dump of memory image of program to run
make verilog MEMORY_HEX_FILE_PATH=./c/fib.hex # Generate Verilog sources
cat ./verilog/Top.v
To run all tests in riscv-tests:
make riscv-tests
Outputs of tests are stored in riscv-tests-results
directory.
To run a specific test case in riscv-tests (when running rv32ui-p-addi
test case):
make ./riscv-tests-results/rv32ui-p-addi.out
To run all tests with C sources in c/
directory:
make c-tests
Outputs of tests are stored in c-tests-results
directory.
To run a specific test case in c-tests (when running fib.c
test case):
make ./c-tests-results/fib.out
To run all tests with Rust sources in rust/
directory:
make rust-tests
Outputs of tests are stored in rust-tests-results
directory.
To run a specific test case in rust-tests (when running fib
test case):
make ./rust-tests-results/fib.out
Run docker run
with the uploaded Docker image.
docker run --rm -v $(pwd):/app --workdir /app -t rhysd/riscv-cpu-chisel:latest make riscv-tests
Distributed under the MIT license.