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SpinalHDL - v1.10.2a Latest Release

Published by Dolu1990 4 months ago

Fix Verilator support (some 5.0+ versions were crashing)

SpinalHDL - v1.10.2

Published by Dolu1990 4 months ago

What's Changed

Fix RegIf SpinalEnum by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1300
regif intr-Factory add MASK split SET/CLR feature by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1329
Compile tester with compiler plugin in Mill by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1325
StreamMux with stream select use join by @g0t00 in https://github.com/SpinalHDL/SpinalHDL/pull/1308
Handle Quotes in Attribute values by @g0t00 in https://github.com/SpinalHDL/SpinalHDL/pull/1333
Some little change on inout signal by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1319
Add exit() to StateMachine class by @AtaraxiaZ in https://github.com/SpinalHDL/SpinalHDL/pull/1332
make cutLongExpressions optional by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1338
RegIf: Fix invalid HTML in DocTemplate by @Tectu in https://github.com/SpinalHDL/SpinalHDL/pull/1348
Axi4Master fixes by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1345
UnionElement simGet by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1344
BlackBox Generic update by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1356
update links for chinese documentation. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1357
Resize StateDelay cycleCount, fixing width mismatch by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1362
Add messages to asserts in Utils by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1361
Report when a timeout has happened for BusSlaveFactory.readStreamBlockCycles by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1351
If the output is not connected, set it to be an empty pair of parentheses by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1339
Proof of concept for isunknown usage by @jdavidberger in https://github.com/SpinalHDL/SpinalHDL/pull/1352
Tilelink mapping rework by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1305
AXI lite simulation master by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1370
Add CountLeadingZeroes utility function by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1359
Allow bus slave factory to read mem with an offset by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1371
Fix corner case of readStreamBlockCycles by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1367
Wishbone bus bugfixes by @jdavidberger in https://github.com/SpinalHDL/SpinalHDL/pull/1312
Inline output signal by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1374
Rename FlowByCCToggle, deprecating the old name by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1360
Add tag to keep I/O unchanged in InOutWrapper by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1373
Fix simulator flags not passed to elaboration for GHDL by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1363
Fix typos in Phase.scala by @IanBoyanZhang in https://github.com/SpinalHDL/SpinalHDL/pull/1385
Fix bin files passed to .sby read statement by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1389
inline more output signal, such as .xxx(xxx[0]) by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1383
add an option to remove timescale by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1388
Add test for formal with RAM initial contents by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1390
add system verilog interface support by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1364
couple of minor optimize for verilog code format by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1393
Update SdramCtrl.scala by @march1993 in https://github.com/SpinalHDL/SpinalHDL/pull/1395
Priority mux by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1377
Moving simulation temporary builds to Workspace Path by @mrberman87 in https://github.com/SpinalHDL/SpinalHDL/pull/1394
avoid to use unnamed workspace name while do formal verification. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1397
Add offset field to generated regif json by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1400
Add wave prefix for verilator & VCS by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1402
fix sv Interface filelist error by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1403
AFix: Adding a few QFormat helpers by @mrberman87 in https://github.com/SpinalHDL/SpinalHDL/pull/1399
Fix verilator version parsing by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1401
Add BRAM RegIf support; Add BRAMDriver by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1386
Fix spaces in file paths for sby generation by @fayalalebrun in https://github.com/SpinalHDL/SpinalHDL/pull/1412
use a simplified and unified method to get class name. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1413
jtagvpi: Don't use blocking IO, to avoid blocking the simulation by @rpls in https://github.com/SpinalHDL/SpinalHDL/pull/1350
Streamhistory by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1414
Correct frequency calculation in newSlowedClockDomain by @louiecaulfield in https://github.com/SpinalHDL/SpinalHDL/pull/1423
Change the usage interface of StreamHistory the same as Stream Adapter and Extender. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1418
Update C++ version CFLAGS as Verilator requires C++14 or newer by @saahm in https://github.com/SpinalHDL/SpinalHDL/pull/1428
[regif] feature upgrade refactoring by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1409
[regif] #1409 review close by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1434
inline literal input for some case by @yportne13 in https://github.com/SpinalHDL/SpinalHDL/pull/1437
Verify component without withAsync option with synchronous reset as default. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1435
VexiiRiscv branch merge by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1415
RegIf support Secure TrustZone by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1438
add missing match case for ElabOrderId.getName by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1444
Constraint writer for Xilinx Vivado (reopened: CDC rework) by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1369
[regif] Ram addr width issue fix by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1447

New Contributors

@AtaraxiaZ made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1332
@Tectu made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1348
@jdavidberger made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1352
@fayalalebrun made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1359
@march1993 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1395
@mrberman87 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1394
@louiecaulfield made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1423
@saahm made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1428

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.10.1...v1.10.2

SpinalHDL - v1.10.1

Published by Dolu1990 9 months ago

What's Changed

Update build.sc dependencies by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1275
VerilatorBackend now cache improvement by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1272
PackedBundle Bug Fix by @dokleina in https://github.com/SpinalHDL/SpinalHDL/pull/1271
Fix comments for trait BitwiseOp by @g0t00 in https://github.com/SpinalHDL/SpinalHDL/pull/1281
XSim: better Windows support + add xcix IP import by @oletf in https://github.com/SpinalHDL/SpinalHDL/pull/1246
AXI and AXI-Stream simulation bus masters by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1288
driveStream on BusSlaveFactory by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1289
allow CounterFreeRun to take bitCount by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1292
add setOutputAsReg by @KireinaHoro in https://github.com/SpinalHDL/SpinalHDL/pull/1293
scala 2.12 is now the default by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1283
Composable exp by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1297
Sim test folder by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1279

New Contributors

@KireinaHoro made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1275
@g0t00 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1281
@oletf made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1246

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.10.0...v1.10.1

SpinalHDL - v1.10.0

Published by Dolu1990 10 months ago

This release integrate the new pipelining API (spinal.lib.misc.pipeline) which is documented here :

https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/introduction.html

What's Changed

Fix hierarchy violation error for toplevel by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1231
reduce size of the generated verilog for resize/access expressions by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1242
Merge bus-fabric branch back to dev by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1244
Add lib.misc.pipeline + lib.misc.plugin API by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1240
disable scalafmt action by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1243
pipeline API SignalKey / Connector refractoring by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1250
Include blackbox sources in formal verification output by @C-Elegans in https://github.com/SpinalHDL/SpinalHDL/pull/1257
Composable exp PR of doom by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1268
Idsl moduledef by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1269
Composable exp by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1270

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.9.4...v1.10.0

SpinalHDL - v1.9.4

Published by Dolu1990 12 months ago

What's Changed

Use simProxy for driving clock by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1175
An experimental PR to use docker image github provided as a CI environment. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1099
Improve error messages for <> by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1186
Move DDR controller sim to tester to keep it updated. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1189
Reg Chead mask and shift don't print when field width equal to busdata width by @xiaozhulanshan in https://github.com/SpinalHDL/SpinalHDL/pull/1126
Fix PackedBundle unpack element bounds filter by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1187
move tests to speed up ci. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1192
move tests into core test. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1197
Bug fix for #1190: VCS run flag not pass to simv by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/1202
DFI Interface by @LurenAA in https://github.com/SpinalHDL/SpinalHDL/pull/1183
Add convenience overloads for sleep/forkStimulus by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1208
Add init parameter to Timeout by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1207
Update C++ version for verilator (to C++14) by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1210
Fix signal name typos by @IanBoyanZhang in https://github.com/SpinalHDL/SpinalHDL/pull/1212
Add option for IO instantitation to InOutWrapper by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1215
Update built Scala minor version to latest by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1218
Bus fabric by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1223
fix the signedDivider component bugs by @xie-1399 in https://github.com/SpinalHDL/SpinalHDL/pull/1220
Iconnectable by @xueweiwujxw in https://github.com/SpinalHDL/SpinalHDL/pull/1073
Added explicit net types to verilog ports by @RiceShelley in https://github.com/SpinalHDL/SpinalHDL/pull/1228
Fix signal names with $ for verilator by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1230

New Contributors

@LurenAA made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1183
@IanBoyanZhang made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1212
@xie-1399 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1220
@xueweiwujxw made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1073
@RiceShelley made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1228

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.9.3...v1.9.4

SpinalHDL - v1.9.3

Published by Dolu1990 about 1 year ago

Mostly 3 important things :

Fix Apb3CC metastability when empty
Prevent Verilator from silently exiting the app on $finish (assertion)
Fix broken scalatic jar dependency giving issues at compilation

Note that Verilator upstream itself may have an issue with clock edges at time 0 :
https://github.com/verilator/verilator/issues/4424

New Contributors

@ZhaokunHu made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1079
Generate diagrams based on SpinalHDL code by @ZhaokunHu in https://github.com/SpinalHDL/SpinalHDL/pull/1079

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.9.2...v1.9.3

SpinalHDL - v1.9.2

Published by Dolu1990 about 1 year ago

Mostly fixes, but also add the new "reader" API, see the https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Advanced%20ones/slots.html#slots demo (on the bottom, "reader")

What's Changed

[regif] AXI-lite4 Rdata BugFix by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1168
spinal.lib.bus.fabric reusable base classes by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1160

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.9.1...v1.9.2

SpinalHDL - v1.9.0

Published by Dolu1990 about 1 year ago

! This release fix the StreamFifoCC from leaking metastable io.pop.payload when empty !

What's Changed

Improve formal verification on fifo-rework by @likewise in https://github.com/SpinalHDL/SpinalHDL/pull/1146
Add tilelink support + many little improvements by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1148
Fifo rework by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1150
Fifo rework by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1149
retide the verification code for StreamTransactionExtender. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1151
VivadoFlow: Fix issues with getFMax() and getArea(), and improve. by @likewise in https://github.com/SpinalHDL/SpinalHDL/pull/1154
Fix StreamFifoCC from leaking metastable io.pop.payload when empty by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1167

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.8.2...v1.9.0

SpinalHDL - v1.8.2

Published by Dolu1990 over 1 year ago

What's Changed

fix check for wide signals by @jonnykl in https://github.com/SpinalHDL/SpinalHDL/pull/1074
feat(lib): add Stream Unpacker by @dokleina in https://github.com/SpinalHDL/SpinalHDL/pull/814
PhysicalUnit formatting by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1075
Disable setAffinity on Windows platform by @kazutoiris in https://github.com/SpinalHDL/SpinalHDL/pull/1093
RegIf update by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1097
Calculate ice40 pll by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1080
Use element width for PackedBundle width by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1101
Compile for all supported versions during CI by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1102
Propagate tags from Tristates when using InOutWrapper by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1088
Packed Word Bundle by @dokleina in https://github.com/SpinalHDL/SpinalHDL/pull/1038
add explicit unsupported feature error of axi4 downsizer. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1103
Release docker images for each version while tag is pushing. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1098
Regif Chead union struct name add prefix by @xiaozhulanshan in https://github.com/SpinalHDL/SpinalHDL/pull/1113
Scala 2.13 build fixes by @dlmiles in https://github.com/SpinalHDL/SpinalHDL/pull/1114
Update LICENSE by @Xorlent in https://github.com/SpinalHDL/SpinalHDL/pull/1112
Deprecate genIf by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1118
feature: add Jtag VPI support for sim by @allexoll in https://github.com/SpinalHDL/SpinalHDL/pull/1095
Fix HDL names of memory ports by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1119
Make type of register value in CHeaderGenerator configurable by @C-Elegans in https://github.com/SpinalHDL/SpinalHDL/pull/1121
core: RFC object SmtBmcSolver extends Enumeration: TYPOs ? by @dlmiles in https://github.com/SpinalHDL/SpinalHDL/pull/1120
Add setAll() and clearAll() for Data by @MarekPikula in https://github.com/SpinalHDL/SpinalHDL/pull/1078
Rework PackedBundle packing to avoid width confusion by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1124
Reset AxiLite4Driver on instantiation by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1139

New Contributors

@xiaozhulanshan made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1113
@dlmiles made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1114
@Xorlent made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1112

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.8.1...v1.8.2

SpinalHDL - v1.8.1

Published by Dolu1990 over 1 year ago

Finaly out <3

What's Changed

Fix literal comp range check by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/989
Make APB3CCToggle sensitive to PSEL by @distributed in https://github.com/SpinalHDL/SpinalHDL/pull/990
publish tester library locally. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/992
#985 Move from @[file row:col] to @ file row by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/993
feat: add comparison operators to PhysicalNumber by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/997
feat: add ECP5 EHXPLLL blackbox and some helper functions by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/995
ci: fix missing iverilog error by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/1000
AxiLite4: Add read only and write only driver classes by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1007
feat(regif): apb4 support and busif improvment by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/976
fix: fix OS version to ubuntu20 and revert to build iverilog into cache. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1009
fix: fixes getFanOut; adds test for data analyzer by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/994
build: upgrade dependency versions by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1016
ci: cache management + code organization by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/1017
Axi4: Add extra helper methods by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1023
ci: fix push-docs by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/1019
Fix crash when Mem word type is zero bits by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1026
Implement addRunFlag(), needed by GHDL. by @likewise in https://github.com/SpinalHDL/SpinalHDL/pull/1028
Naxriscv by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1032
Add GHDL sim backend support for different waveform formats. by @likewise in https://github.com/SpinalHDL/SpinalHDL/pull/1033
feat(lib): Axi4 to AxiLite4 conversions by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1002
fix the missing tester package while publishing locally. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1034
[regif] resevedAddress default value configable by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1035
regif parasiteFieldAt method added by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1037
[regif] fix readData hold issue for the reason of security by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/1039
[Fix] fix typo by @chenbo-again in https://github.com/SpinalHDL/SpinalHDL/pull/1043
Axis width fixes by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/1041
Fix resized data handling in tuple assignment by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1045
Make SpinalFormalConfig members class parameters by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1055
Fix subdivideIn(..., n bit) for corner cases by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1051
Set the correct reset signal type (polarity) in QSys IP file by @tlupick in https://github.com/SpinalHDL/SpinalHDL/pull/1059
Retide the generated files by tester/test cases. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/1053
Add testcases for analog connections by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1062
Fix cocotb test cases by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/1065
Inout fix by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/1046
[Fix] polish AhbLite3Interconnect example in comment which can not co… by @chenbo-again in https://github.com/SpinalHDL/SpinalHDL/pull/1064

New Contributors

@chenbo-again made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/1043

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.8.0...v1.8.1

SpinalHDL - v1.8.0b

Published by Dolu1990 almost 2 years ago

Fix SpinalEnum not being usable outside SpinalHDL context

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.8.0a...v1.8.0b

SpinalHDL - v1.8.0a

Published by Dolu1990 almost 2 years ago

What's Changed

Fix literal comp range check by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/989
Make APB3CCToggle sensitive to PSEL by @distributed in https://github.com/SpinalHDL/SpinalHDL/pull/990
publish tester library locally. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/992
#985 Move from @[file row:col] to @ file row by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/993
no more @[file row:col] comment generated by default in the RTL

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.8.0...v1.8.0a

SpinalHDL - v1.8.0

Published by Dolu1990 almost 2 years ago

What's Changed

feat(WhenBuilder): add WhenBuilder by @tanhongze in https://github.com/SpinalHDL/SpinalHDL/pull/868
FormalDispatcherSequencial by @andyspace in https://github.com/SpinalHDL/SpinalHDL/pull/856
FormalDeMuxTester by @andyspace in https://github.com/SpinalHDL/SpinalHDL/pull/855
FormalMuxTester by @andyspace in https://github.com/SpinalHDL/SpinalHDL/pull/854
FormalForkTester by @andyspace in https://github.com/SpinalHDL/SpinalHDL/pull/842
integrate internal logic assertion into StreamFifoCC. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/871
perf: make UIntToOh faster in simulation by @tanhongze in https://github.com/SpinalHDL/SpinalHDL/pull/874
docs: add links to RTD for Counter by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/830
gitignore: ignore project/{project,metals.sbt} by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/880
Fix bug: only top rtl present in rtl source paths when oneFilePerComponent enable. by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/882
fit the naming policy. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/883
add formal verify for axi4readonly datas by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/774
Formal name policy updates. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/884
Simulation support time precision by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/843
remove storage/ + todo.md by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/907
refactor: isEquals -> isEqualTo by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/910
add toBytes to get fixed bytes from BigInt. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/898
Add SystemRDL RegIf exporter by @MarekPikula in https://github.com/SpinalHDL/SpinalHDL/pull/900
Allow braces by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/906
add createSelector to Mux and Demux IO. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/901
Rework on VCS Flags by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/911
Lib: Add PackedBundle by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/889
feat(lib): add Axi4Unburster by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/821
build: fix simple warnings by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/914
Hide ci by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/908
fix(sim): Verilator time precision by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/921
Axi4 sim agent fixes by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/924
add gitter channel for chinese. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/925
docs(readme): prefix gitter links with corresponding lang by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/926
docs(readme): remove outdated Travis build status by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/928
ci: update vendor actions by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/917
fix: regif PSLVERROR bug fix by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/915
build: update plugin.sbt by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/938
feat: add bus factory error signals by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/927
tests: add formal tests to StreamJoin by @andyspace in https://github.com/SpinalHDL/SpinalHDL/pull/876
tests: add formal tests to StreamArbiter by @andyspace in https://github.com/SpinalHDL/SpinalHDL/pull/875
ci: scaladoc to gh-pages by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/918
feat: add some utilities that can help analyze the circuit structure by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/916
ci: add scalafmtCheck step by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/936
feat: add Latch and LatchWhen by @dokleina in https://github.com/SpinalHDL/SpinalHDL/pull/944
ci: do not check fmt lint on dev by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/953
feat: add port keyword by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/935
feat(sim): let randomize() return the new value by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/940
docs: add help for contributors by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/909
ci: use scala 2.12 with unidoc by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/959
ci: update actions by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/960
fix API reference documentation by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/962
feat(lib): debug over Intel Virtual JTAG by @LYWalker in https://github.com/SpinalHDL/SpinalHDL/pull/950
Create FUNDING.yml by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/966
Add sequential gray encoding for enum by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/967
test: add RegIf unit tests by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/945
fix: StreamFragmentWidthAdapter(x, y, true) widthOf(y) = 2 * widthOf(x) by @likewise in https://github.com/SpinalHDL/SpinalHDL/pull/964
Make SpinalSim seed default random again by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/971
fix cocotb problem while runing on system with different language. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/974
Add support for mill build. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/969
fix: xfix mux by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/970
Axi4: Add Axi4IdRemover and tests by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/812
Deprecate Bool without braces by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/975
build: clean and add tester module to releases, move SpinalFormalFunSuite in it by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/980
fix: typo in XSim wave format error message by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/983
feat: BU and BS string prefixes by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/981
Add Vhdl/Verilog assignements comments to traceback to the original Scala code by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/985
Enum merge by @Dolu1990 in https://github.com/SpinalHDL/SpinalHDL/pull/984
fix: SimBigIntPimper toBytes by @andreasWallner in https://github.com/SpinalHDL/SpinalHDL/pull/979

New Contributors

@andyspace made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/856
@dokleina made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/944
@LYWalker made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/950
@likewise made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/964

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.3...v1.8.0

SpinalHDL - v1.7.3a

Published by Dolu1990 about 2 years ago

This hotfix chery pick a few things from dev :

365f57ac Fix Verilator backend rtlIncludeDirs on windows
9d20166c mergeRTLSource can now override the input safely #851 Dolu1990 09/20/2022 10:37 AM
56400992 fix #863 Add allowOutOfRangeLiterals(my4bits === 42) to skip error. Also add SpinalConfig(allowOutOfRangeLiterals = true) to apply it everywhere

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.3...v1.7.3a

SpinalHDL - v1.7.3

Published by Dolu1990 about 2 years ago

The main purpose of this release is to fix a bug affecting the generation of tristate signals.

What's Changed

fix the error generated by xsim emulation of xilinx ip for different devices by @liuwei9 in https://github.com/SpinalHDL/SpinalHDL/pull/801
move SpinalFormalFunSuite to spinal lib. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/802
Add formal verification cases on StreamTransactionCounter and StreamTransactionExtender by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/808
Temperal fix the aggressive prune signal feature of yosys. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/815
RTL merge fixes by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/810
Add AvalonST basic support by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/791
[regif] fix RC Bool() assignFromBits assert issue fix by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/819
expose timeout counter to formal verification facility. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/822
skip formal verification while CI. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/826
add no delay function to transaction extender by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/827
XSim: Overhaul XSI interface and make it signal width aware by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/831
fix past valid definition. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/824
XSim add custom simulation script and flag support by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/838
move wait sampling while pending_reads is empty. partially fix #839 by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/840
lib: Add 8b10b encoding by @dnltz in https://github.com/SpinalHDL/SpinalHDL/pull/788
RegIf update by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/850
Add GlobalClock and an example for async verfication. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/847

New Contributors

@liuwei9 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/801

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.2...v1.7.3

SpinalHDL - v1.7.2

Published by Dolu1990 about 2 years ago

Mostly, this fix a crash when generating blackbox in verilog with one file per component enabled

What's Changed

[regif] fix UNASSIGNED REGISGTER Warning for Reserved bits by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/792
Align inout port in Verilog generation by @MarekPikula in https://github.com/SpinalHDL/SpinalHDL/pull/795

New Contributors

@MarekPikula made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/795

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.1...v1.7.2

SpinalHDL - v1.7.1

Published by Dolu1990 over 2 years ago

What's Changed

Prove for fifo. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/706
#671 rollback by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/710
AFix: Improve range alignment when saturating by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/709
Reduce the load of CI by moving verification of controllable fifo to tester as an App. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/707
Regif update by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/713
add back to back test to fifo. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/714
Fix execute simulation fail on Windows 11 by @kazutoiris in https://github.com/SpinalHDL/SpinalHDL/pull/718
regif address hit naming optmize by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/722
Add Axi4StreamWidthAdapter by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/697
fix #725 by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/728
RegIf: Restructure descriptors by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/726
Fix VPI include flags and path string on Windows by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/737
Fix wishbone arbitration by @Jeff-Ciesielski in https://github.com/SpinalHDL/SpinalHDL/pull/708
Add synopsys_sim.setup and other environment setup support by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/747
Add pendingMax parameter to Axi4CrossbarFactory by @tlupick in https://github.com/SpinalHDL/SpinalHDL/pull/752
[AXI4ASLAVEFACTORY] support for useID=false by @sabbari in https://github.com/SpinalHDL/SpinalHDL/pull/720
Bitwise operators for Vec by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/750
Add readWriteSyncPort to MemPimped by @tanhongze in https://github.com/SpinalHDL/SpinalHDL/pull/740
rename withPast to pastValid to clearify the target. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/755
AFix: Switch to spinal sim, upgrade some rounds by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/759
Test vec bitwise ops by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/762
fix speed of the Verilog component emitter by @jonnykl in https://github.com/SpinalHDL/SpinalHDL/pull/763
Try to add some formal assertion for common cases. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/721
docs: add reminder: process always after states by @numero-744 in https://github.com/SpinalHDL/SpinalHDL/pull/765
Add a more convenient repeat data API. by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/760
fix(sim): fix bad classpath when invoked from Mill by @huaixv in https://github.com/SpinalHDL/SpinalHDL/pull/772
rename formal functions to distinct Master and Slave ends. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/771
XSim: Add missing t_fp_xsi_get_time type by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/751
AFix updates and improvements by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/767
Call compositAssignFrom on Vec elements to propagate compositeAssign hook by @Dijky in https://github.com/SpinalHDL/SpinalHDL/pull/768
Add missing MemSymbolsTag in the VHDL emitter by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/738
Add AFix rounding range tests by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/777
Afix update, some bug fix and some features are added. by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/776
Sim: Fix pow10 off-by-10 bug by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/782
fix axiMemorySim data.drop() bug by @hanm2019 in https://github.com/SpinalHDL/SpinalHDL/pull/784

New Contributors

@kazutoiris made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/718
@tlupick made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/752
@sabbari made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/720
@numero-744 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/750
@huaixv made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/772
@Dijky made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/768
@hanm2019 made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/784

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.7.0...v1.7.1

SpinalHDL - v1.7.0

Published by Dolu1990 over 2 years ago

v1.7.0

Two new main features :

Formal verification is now in a good state

SymbiYosys integration, ex FormalConfig.withBMC(15).doVerify(..)
Added anyconst/anyseq/... support
Documented in https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html

AFix floating point added (experimental, subject to changes)

Unifie unsigned/signed handeling
Tracking the exact range of possible values

And many other additions and fixes !

Auto generated change log from github :

What's Changed

add TupleBundle by @pwang7 in https://github.com/SpinalHDL/SpinalHDL/pull/615
fix #617 of OS seperator char issue by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/618
readme version update by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/622
add test cases for axi4 bus downsizer and on chip ram. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/624
Correct MaskMapping hit() function by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/630
add pipelined function to support timing optimization. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/623
rename stream function '~~' to map by @pwang7 in https://github.com/SpinalHDL/SpinalHDL/pull/632
add driver to flow for simulation. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/645
add basic support for synopsys vcs by @name1e5s in https://github.com/SpinalHDL/SpinalHDL/pull/644
VCS FSDB-wave dump supported by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/650
VCS advanced features support by @wswslzp in https://github.com/SpinalHDL/SpinalHDL/pull/651
Axi4SlaveFactory: writeHaltRequest stall on last burst txn by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/662
add basic support for vivado's xsim on linux by @name1e5s in https://github.com/SpinalHDL/SpinalHDL/pull/664
add order parameter for StreamWidthAdapter with corresponding test. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/656
Use scalafmt to format code by @jiegec in https://github.com/SpinalHDL/SpinalHDL/pull/539
Add loongarch64 support by @cheungxi in https://github.com/SpinalHDL/SpinalHDL/pull/670
Add basic Axi4 Stream support by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/661
Unify fixed-point into a single class - Rewrite by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/566
Fix assertion in wishbone >> operator by @Jeff-Ciesielski in https://github.com/SpinalHDL/SpinalHDL/pull/637
AvalonMMSlaveFactory: allow byteEnable to be used by @nbstrike in https://github.com/SpinalHDL/SpinalHDL/pull/679
Try to implement a comparison on UInt with wrapping nature. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/675
Minor axi4 updates by @dnltz in https://github.com/SpinalHDL/SpinalHDL/pull/682
Add a check method to Stream. by @losfair in https://github.com/SpinalHDL/SpinalHDL/pull/673
regif some issue fix by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/683
Add map and translate payload shortcuts to Flow by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/684
shuffle function for Vec. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/681
Interrupt Register Interface on regif redesign by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/688
Fix #659 AxiMemorySim for AXI4 specification by @tanhongze in https://github.com/SpinalHDL/SpinalHDL/pull/672
fix CHeader addrLength=0 bug by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/690
Add SlaveFactory Constructor by @NomadShen in https://github.com/SpinalHDL/SpinalHDL/pull/691
RFC: Axi4S: Make AxiS type a subclass of stream for overrides by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/685
discard issue catching from oshi on M1 Mac by @allexoll in https://github.com/SpinalHDL/SpinalHDL/pull/671
regif new filed API support HardType by @jijingg in https://github.com/SpinalHDL/SpinalHDL/pull/693
Don't generate VHDL port list when there are no ports defined by @kleinai in https://github.com/SpinalHDL/SpinalHDL/pull/696
initially add FormalConfig which call symbiyosys with yices as default solver. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/692
Remove whitespaces in generated verilog files by @dnltz in https://github.com/SpinalHDL/SpinalHDL/pull/701
lib: bus: amba4: Axi4ToApb3: Ignore writes without strb by @dnltz in https://github.com/SpinalHDL/SpinalHDL/pull/700
formal example with prove and cover mode for Limited Counter. by @Readon in https://github.com/SpinalHDL/SpinalHDL/pull/704
Fix path issue in formal code by @wifasoi in https://github.com/SpinalHDL/SpinalHDL/pull/705

New Contributors

@name1e5s made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/644
@cheungxi made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/670
@losfair made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/673
@tanhongze made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/672
@NomadShen made their first contribution in https://github.com/SpinalHDL/SpinalHDL/pull/691

Full Changelog: https://github.com/SpinalHDL/SpinalHDL/compare/v1.6.4...v1.7.0

SpinalHDL - v1.6.4

Published by Dolu1990 over 2 years ago

v1.6.4

Mostly 3 fixes :

Nameable.composite now handle the ref owner properly
Fix cross clock pop reset for active low restets
Emited VHDL now check for bit access being out of range

In bulk :

Add Bool.asSInt(bitCount)
Vhdl package now check against out of bound
improve component definition name overlap error report
Add SEL handling to WishboneSlaveFactory
Fix asyncAssertSyncDeassertCreateCd reset polarity
add more test configs for the StreamFifoCcTester
#609 add SpinalReport.printZeroWidth()
#608 add Stream.forkSerial
Fix #610 (removePruned=true removing too much)
Add Axilite4 plic/clint
Add support for verilog simple dual port read first
add Any.ifMap(cond)(T => T)
improve the axi4ram design by pipeline stream
use show ahead pattern instead of plain logic.
use queue to break down the bStream and writeStream.
Verilog backend can now emit mux's switch with single target without using begin end
Add mssing code (Nameable.setPartialName with owner)
Add wishbone plic/clint
Add AxiLite4SpecRenamer for read only
Area vallCallbackRec is now able to properly override ref owner

SpinalHDL - V1.6.2

Published by Dolu1990 over 2 years ago

V1.6.2

Mostly fixes with a some additions

Verilog backend now implement a better randboot
add OHMasking.roundRobinMaskedInvert
LatencyAnalysis now assert no null arguements
Component postInitCallback now enforce the clockdomain
MemReadPort.bypass added
Regif merged
Fix SpiXdrMasterCtrl definition name being forced
Fix generation of RTS and CTS pins for UartCtrl
SwitchStatement.normalizeInputs fixed for scala 2.13.7+
SpiXdrMasterCtrl can now be used for more than 8 bits SPI frame and mixed width configurations
Fix non trivial verilog fixed signal are emited by using function (fix sim)
StateMachine build can now be manualy enforced
Fix Scope property push when never set by the past and no default
Fix a few ScopeProperty restore/rework
add more option to axi4 unburstify.
support useSize = false to axi4 unburstify.
Verilator backend no more copy rom bin files to the current directory.
Add downsizer for Axi4
JtagInstructionWrapper.ignoreWidth added to handle jtag chain (openocd updated too)
Component stub clock/reset removed bug fix
Backends do not check anymore the definition name uniquness of blackboxes (#546)
Add reset function to Axi4 related simulation agents.
Add more Symplify api
Add OhMux
Binary system utils added
Add globalCache(key, factory)
Fix scala 2.13 Apb3Decoder Seq
Fix #553 Verilog /* xx */ for CD BOOT kind
spinal.lib add Repeat(Data, times)
Axi4SlaveFactory now buffer the write responses to avoid some combinatorial link between streams
spinal.lib now implicitly add withBufferedResetFrom function to ClockDomain
add BitVector orMask/andMask