SpinalHDL

Mostly fixes and small feature additions

• Mem with only 1 entry (translated into register) now allow multiple write ports (allow override)
• add OHMasking.roundRobinMaskedFull
• add OHMasking.roundRobinMasked
• StateFsm now give name to the inner states
• add axi4 bus support to Axi4ReadOnlyMonitor.
• Add AreaRoot
• Add checks to ensure the memory and its ports are correct hearchicaly speaking
• Fix BmbToAxi4Bridge
• add ScopePropertyContext with mutable and immutable map for better scaling
• Add BufferCC.defaultDepth scopeProperty
• Add support for write byte enable in BusSlaveFactory.writeMemWordAligned
• added BUFGCE (bufg with clock enable) to clocking blackboxes for xilinx
• Add lib.logic to infer decoding logic from some Masked specification
• MuxOh now check that inputs have the same length
• Better Reserved name not free reporting
• BitVector.subdivide now have a strict option for non multiple bit lenght
• Add AreaObject
• Add StreamTransactionExtender.
• Add setIdle and setBlocked functions to the axi buses,
• spinal.lib now add Seq.groupByLinked
• Fix AxiLite4 responses getters
• MemWrite fix data width check
• Add Module alias to Component in spinal.core
• Prevent enum's mux normalizeInputs being applied to the selection exception
• Add read/write instructionCtrl to JtagTap that allows for different Input/output data
• add Growable.addRet(value)
• add Mem.readAsyncPort
• unassigned register with init will now emit a error on the first elaboration
• add TraversableOnce.distinctLinked
• ValCallbackRec can now name LinkedHashSet
• add Data.wrapNext
• Add Data.freeze() to error on any future assigment
• add log2up(Int)
• PhaseMemBlackboxing now implement wrapConsumers and removeMem
• Add ScopeStatement.on(body)
• Fix ClockDomain.apply
• Can now apply tags to ClockDomain
• Add ClassName object
• Add ScopeProperty(defaultValue) construction
• Add Mem.fill API
• always emit timescale in verilog
• fix #520 640x480#60 hz vga timings
• deprecated BitVector.range, replaced by bitsRange
• add BitVector.valueRange
• StreamFifoLowLatency can now use Vec based storage
• SpinalSim iverilog can now use includes
• SpinalSim now try to figure out if a exception came for the hardware elaboration API
• support inline rtl for BlackBox
• Move lib.generator.Lock to core.fiber
• Add xilinx s7 ff blackbox
• Add MuxOH.or
• Axi4Crossbar fix addPipelining being applied twice for nodes which are both master and slave at the same time
• Remove Axi4Decoder low latency support
• Fix Axi4 write decoders when used in low latency mode
• Axi4 now handle better the absence of burst signal and id signl
• Revert Verilog backend Mem.read multi symbole ram changes (no more xxxx[y : z]) to help inferation
• Fix jtagTap bypass (thanks sebastien-riou)
• UsbDeviceCtrlTester do not try isochronus on EP0 anymore
• Add OhMasking.firstV2
• Component.propagateIo removed (in favor of Data.toIo)
• verilog reduction operators now handle zero width signals
• Fix empty MultiData comparison
• StateMachine whenIsActive now implement priorities.
• States implementing the StateCompletionTrait should use whenIsActive with priority 1 to ensure they are called last.
• StateMachine.bootAsEntry renamed into makeInstantEntry
• Added some size check to Apb3Decoder
• Merge branch 'SpinalHDL:dev' into dev
• Add Bool ? T otherwise T
• add cache for verilator binaries
• SpinalSimConfig.compile do not mutate the config anymore
• Fix ClockDomainResetGenerator.powerOnReset default value
• Add support to give name to Option[Nameable]

v1.6.0

This version has 3 main things :

1. It fix some clockdomain crossing issues in the StreamCcByToggle and FlowCcByToggle.
2. It add Scala 2.13 support
3. Because of the scala 2.13 support and the preparation for scala 3 support, it has to drop some syntax. Now if you want do define a Bool signal, you need to write Bool() / in Bool() / out Bool()

It also fix the Axi.incr issues with verilator, the ethernet cross clock domain and a few other things.

This update bring many fixes and improvement, notably :

1. Better naming

There will now be much less unamed signals in the generated netlists.
In addition, the Composite class feature was added to define relative namespace in a smooth way.

See https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Structuring/naming.html# for more information and examples.

2. Fiber API

This allow to generate hardware using a similar paradigm than the Scala Future.

See https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Libraries/fiber.html for more info.

3. A USB OHCI controller (usb host low/full speed)

v1.4.0

Important, this new version now use a scala compiler plugin to improve internals of the language. Consequently, you need to enable that plugin in your project, to do so in SBT, see :
https://github.com/SpinalHDL/SpinalTemplateSbt/blob/b524ddddd830d7e9e7d76604b0d593bb897c7229/build.sbt

Another API change is the removal of implicit String to B/U/S convertion, so you can't do anymore (myUInt + "0001"), instead you have to do (myUInt + U"0001").

Other changes are :

• SpinalSim now support directories with spaces
• Verilator compilation is now multithreaded
• Fix SpinalSim seed
• lib.Bench now use a environnement variable by default
• Remove deprecated doManagedSim
• Improve doSim API
• added ECP5 JTAGG Blackbox
• synthesis targets now use environnement variable to find tools path
• Fix I2cCtrl SDA/SCL driving
• Fix SpinalSim.addRtl on windows
• Add Component.afterElaboration as a clean replacement of addPrePopTask
• Better verilog formating
• Bits method extention
• Stream add clearValidWhen
• AhbLite3 incr beatCounter only when HTRANS == SEQ or NONSEQ
• Add a few null assert in the expression to have null issues detected at user elaboration time
• Add Anlogic Eagle BRAM to BMB
• improve generator naming using idsl
• Add Long to Bits/UInt/SInt implicits
• SpinalSim add a pre sim dut eval to propagate constants
• BlackBox mapClockDomain now support reset/enable polarity adaptation
• Fix enumeration undeterministic generation order
• Now the default assert severity is FAILURE
• SpinalSim now handle Verilator assertion failure
• UartCtrl now allow more than 255 fifo depth, support break, support CTS RTS
• fix readStreamNonBlocking for multi-word case
• Add StreamMux, StreamCombinerSequential, StreamForkSimple
• Stream::transmuteWith
• Add StreamForkSimple
• Emit proper assert/assume/cover statements in Verilog

• Fix latch/not-assigned detection for components inputs
• If no memory blackboxer is specified in the SpinalConfig, then the default one is added with "on request" policy
• Fix ResetArea