Open Source Verification Bundle for VHDL and System Verilog
APACHE-2.0 License
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Verification Condition Generator
List of awesome open source hardware tools, generators, and reusable designs
