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virtual
argument to TLBEntry.sectorHit
function (https://github.com/chipsalliance/rocket-chip/pull/2952)IncoherentBusTopology
to support multiclock and custom clocking (https://github.com/chipsalliance/rocket-chip/pull/2940)RocketTiles
into separate PRCI groups (https://github.com/chipsalliance/rocket-chip/pull/2842)WithHypervisor
config (https://github.com/chipsalliance/rocket-chip/pull/2946)PROT_PRIVILEDGED
- This was a typo. It is now PROT_PRIVILEGED
. (https://github.com/chipsalliance/rocket-chip/pull/2925)BuildHellaCache
key (https://github.com/chipsalliance/rocket-chip/pull/2919)PTE_RSVD
was introduced into Spike in riscv-software-src/riscv-isa-sim#750pf
to PTWResp
and TLBEntryData
to pipe this through.sfence.bits.hg=1, hv=0
only target TLB entries with V=1 (and not V=0) (https://github.com/chipsalliance/rocket-chip/pull/2954)toaxe.py
to python3 (https://github.com/chipsalliance/rocket-chip/pull/3034)AsyncClockGroupsKey
a node generator (https://github.com/chipsalliance/rocket-chip/pull/2935)debug
module name to tlDM
(https://github.com/chipsalliance/rocket-chip/pull/3029)x
register whose numeric specifier coincides with a previous instruction's f
register. (https://github.com/chipsalliance/rocket-chip/pull/2945)rocc_illegal
to use reg_vsstatus.xs
field (https://github.com/chipsalliance/rocket-chip/pull/2983)aux_pte.reserved_for_future
whenever ``aux_pte.ppn` is driven (https://github.com/chipsalliance/rocket-chip/pull/3003)haveFSDirty
(https://github.com/chipsalliance/rocket-chip/pull/2997)RoccBlackBox
with Vivado (https://github.com/chipsalliance/rocket-chip/pull/3035)TraceGen
from `HeterogeneousTileExampleConfig (https://github.com/chipsalliance/rocket-chip/pull/2923)Published by sequencer about 2 years ago
mcountinhibit(0)
=== 1 (#2700)subWordBits
param to support subbanking (https://github.com/chipsalliance/rocket-chip/pull/2645)singleIn
and singleOut
with typeTagIn
and typeTagOut
RegFieldDesc
(#2685)ResetCrossingType
and use with BlockDuringReset
in TilePRCIDomain
(https://github.com/chipsalliance/rocket-chip/pull/2641/)
ClockCrossingType
. Currently, there are two crossing types: NoResetCrossing
and StretchedResetCrossing(cycles: Int)
Blockable
utilClockCrossingReg
IntXing
in a synchronize
method with to
and from
methodsval tiles
in trait HasTiles
is now populated eagerly via the TilesLocated
Field. (https://github.com/chipsalliance/rocket-chip/pull/2504)HasHierachicalBusTopology
trait replaced with two config options:
WithCoherentBusTopology
WithIncoherentBusTopology
HasPeripheryBootROM
and HasPeripheryBootROMModuleImp
are removed and replaced by a call to BootROM.attach
BootROMParams
Field is removed and replaced with BootROMLocated
FieldMaskROMLocated
Field is addedSubsystemExternalResetVectorKey
, SubsystemExternalHartIdWidthKey
and InsertTimingClosureRegistersOnHartIds
Fields are addedResetVectorBits
Field is removedHasExternallyDrivenTileConstants
bundle mixin is removedHasResetVectorWire
subsystem trait is removedHasTileInputConstants
and InstantiatesTiles
subsystem traits are addedBaseTile
exposes val hartIdNode: BundleBridgeNode[UInt]
and resetVectorNode: BundleBridgeNode[UInt]
and these are automatically connected to in HasTiles
.rocket.Frontend
, rocket.ICache
, rocket.DCache
, rocket.NDCache
now have BundleBridgeSink[UInt]
for their reset vector or hartid wire inputs.
rocket.HasHellaCache
, you will have to manually connect up those nodes to the aforementioned BaseTile
nodes.master
param to TilePortParamsLike
(https://github.com/chipsalliance/rocket-chip/pull/2634/)TileInputConstant
as an MMIO Address Prefix used in ITIM and DTIM hit calculations (https://github.com/chipsalliance/rocket-chip/pull/2533)
--target-dir
to Config (https://github.com/chipsalliance/rocket-chip/pull/2725)RenameDesiredNames
transform and LintConflictingModuleNames
Lint rule (https://github.com/chipsalliance/rocket-chip/pull/2452)
ElaborationArtefactAnnotation
- an API similar to ElaborationArtefacts
(#2727)
MemoryPathToken
(https://github.com/chipsalliance/rocket-chip/pull/2729)nExtTriggers
a val for compatibility with cloneType (https://github.com/chipsalliance/rocket-chip/pull/2667/)TLToAXI4
metadata code paths into a single path through TLtoAXI4IdMap
TLToAXI4.stripBits
other than 0 illegal and stop using it internally.Annotated.idMapping
and delete associated application and annotation class.base
address argument to constructor https://github.com/chipsalliance/rocket-chip/pull/2628
isShrink
TLPermissions
assertion on C channel to isReport
(https://github.com/chipsalliance/rocket-chip/pull/2675)valid
with earlyValid
and lateCancel
to fix a timing path for A-channel requests (https://github.com/chipsalliance/rocket-chip/pull/2480, https://github.com/chipsalliance/rocket-chip/pull/2488)highestIndexFirst
arbitration policy (https://github.com/chipsalliance/rocket-chip/pull/2587)maxTransactionsInFlight
field https://github.com/chipsalliance/rocket-chip/pull/2627
bundleSafeNow
guard with instantiated
guard (https://github.com/chipsalliance/rocket-chip/pull/2680)BundleBroadcast
into BundleBridgeNexus
(https://github.com/chipsalliance/rocket-chip/pull/2497)
SafeRegNext
to BundleBridgeNexus
to preserve width (https://github.com/chipsalliance/rocket-chip/pull/2520)rotate
for zero-width wires (https://github.com/chipsalliance/rocket-chip/pull/2663)lateValid
and revocableSelect
to shift the deep logic cones from before the valid/selec
registers to after the bitmap
register (https://github.com/chipsalliance/rocket-chip/pull/2673, https://github.com/chipsalliance/rocket-chip/pull/2677)Published by sequencer over 2 years ago