Chisel: A Modern Hardware Design Language
APACHE-2.0 License
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SimulationData.expect
calls now record source location and report it in the FailedExpectationException
on failure..fir
size..readOnly
on any Data
to prevent connections to the returned value. Resolves https://github.com/chipsalliance/chisel/issues/1267.f
to the bits
field of a Valid
instance with the new Valid.map(f)
method.probe.define
to a mismatched chisel type..asTypeOf
would return a Wire
. To get the old behavior, wrap the .asTypeOf
call in WireInit(...)
.n - 1
times 16-bytes for an Aggregate with n
elements..toString
behavior better outside of Chisel elaboration contexts.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.4.0...v6.5.0
Published by jackkoenig 3 months ago
suggestName
method to HasTarget
(by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3881)HasTarget
trait now also exposes suggestName
method of a NamedComponent
.stop
is no longer ignored. The construct was extended to accept Printable.elaborateGeneratedModule
in workspace
parametric (by @rameloni in https://github.com/chipsalliance/chisel/pull/3952)Chiselsim
to configure the workspace with additional args for firtool
(#3932). The user can specify how the sv circuit is compiled for simulation (i.e. including debug information -g
).btor2
for Bounded Model Checking using ChiselStage.emitBtor2
.modulePorts
and fullModulePorts
methods in DataMirror
that returns all ports on an Instance
of a module.SimulationData.expect
calls now record source location and report it in the FailedExpectationException
on failure..fir
size..readOnly
on any Data
to prevent connections to the returned value. Resolves https://github.com/chipsalliance/chisel/issues/1267.f
to the bits
field of a Valid
instance with the new Valid.map(f)
method.probe.define
to a mismatched chisel type.firtool
.chisel3.internal
APIs should never have been public in the first place..getWidth
was inconsistent with the width of the emitted FIRRTL for ChiselEnum
values cast to UInt
.--use-legacy-width
(formerly known as --use-legacy-shift-right-width
). Users are encouraged to build Verilog with and without this option enabled and diff the result to verify that this change in width behavior did not silently affect the correctness of their designs.()
when using it).Bidirectional.Default
and Bidirectional.Flipped
). There are deprecations for the typical APIs.asTypeOf
would return a Wire
. To get the old behavior, wrap the .asTypeOf
call in WireInit(...)
.assume
with the specified format message.when not(predicate): printf(...)
was emitted followed by a message-less assume
.assert
output but specifically uses $error(..)
instead of a printf guarded by the usual printf guards.circt_chisel_ifelsefatal
intrinsics and use it for chisel3.assert emission.SRAM
s updated to directly emit FIRRTL memories (as opposed to creating SyncReadMem
s.PlusArgsTest(x, str)
is now deprecated as first argument is unused. Use PlusArgsTest(str)
.circt_chisel_ifelsefatal
intrinsics and use it for chisel3.assert emission.IntrinsicExpr
instead of IntrinsicModule
n - 1
times 16-bytes for an Aggregate with n
elements.--log-level
to circt.stage.ChiselStage
object circt.stage.ChiselStage
was ignoring the Logger.DataMirror.checkTypeEquivalence
to actually check all fields of Bundles and Records. This may expose latent bugs in user code.SInt
literals (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3943)0
.AssertProperty
failing to fire in verilator simulation..toString
behavior better outside of Chisel elaboration contexts.https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala
should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
jextract
download URL (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3868)layers
for firrtl.instance
(by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3902)make serve
in website/ subdir. (by @mmaloney-sf in https://github.com/chipsalliance/chisel/pull/3947)desiredName
as defname
for extmodule
, specify right convention for modules (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3958)Full Changelog: https://github.com/chipsalliance/chisel/compare/v7.0.0-M1...v7.0.0-M2
Published by jackkoenig 4 months ago
CHISEL_USE_COLOR
. Set to true
to force Chisel to use color and false
to disable it.TERM
to be set to something other than dumb
.SyncReadMem
wrapper is instantiated using a new object, SRAM.apply
, and invokes .write
, .read
, and .readWrite
to generate a desired number of read, write, and read/write ports. This function returns a new Bundle
wire containing the control signals for each requested port.SRAM.apply
and SRAM.masked
now take a contents
parameter, by default a None
, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.SRAM
APIs that take three Clock
sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock
sequence and drive them accordingly.suggestName
API for hierarchy instances.Modules
and Queues
SyncReadMem.readWrite
when explicit clocks are used (backport #3313) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3315)Reg()
to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3778)
DataView
(including FlatIO
)Reg()
https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala
should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
import chisel3._
import chisel3.util._
mikepenz/release-changelog-builder-action
to v4.1.1Full Changelog: https://github.com/chipsalliance/chisel/compare/v3.6.0...v3.6.1
Published by jackkoenig 5 months ago
modulePorts
and fullModulePorts
methods in DataMirror
that returns all ports on an Instance
of a module.0
.AssertProperty
failing to fire in verilator simulation.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.3.0...v6.4.0
Published by jackkoenig 5 months ago
0
.AssertProperty
failing to fire in verilator simulation.Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.2.0...v5.3.0
Published by jackkoenig 6 months ago
DataMirror.checkTypeEquivalence
to actually check all fields of Bundles and Records. This may expose latent bugs in user code.https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala
should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.2.0...v6.3.0
Published by jackkoenig 6 months ago
suggestName
API for hierarchy instances.SRAMInterface
parameters publicly available (backport #3826) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3827)memSize
, dataType
, numReadPorts
, numWritePorts
, numReadwritePorts
, masked
parameters are now visible for SRAMInterface
.Reg()
to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3779)
DataView
(including FlatIO
)Reg()
rm -rf
--log-level
to circt.stage.ChiselStage
object circt.stage.ChiselStage
was ignoring the Logger.DataMirror.checkTypeEquivalence
to actually check all fields of Bundles and Records. This may expose latent bugs in user code.SRAMInterface
address width (backport #3830) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3839)https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala
should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
import chisel3._
import chisel3.util._
mikepenz/release-changelog-builder-action
to v4.1.1Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.1.0...v5.2.0
Published by jackkoenig 8 months ago
suggestName
method to HasTarget
(backport #3881) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3882)HasTarget
trait now also exposes suggestName
method of a NamedComponent
.stop
is no longer ignored. The construct was extended to accept Printable.--log-level
to circt.stage.ChiselStage
object circt.stage.ChiselStage
was ignoring the Logger.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.1.0...v6.2.0
Published by jackkoenig 8 months ago
implicitClock
and implicitReset
that can be overridden within Module
to change what values are used as the implicit clock and implicit reset respectively.SRAMInterface
parameters publicly available (backport #3826) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3828)memSize
, dataType
, numReadPorts
, numWritePorts
, numReadwritePorts
, masked
parameters are now visible for SRAMInterface
.Reg()
to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3780)
DataView
(including FlatIO
)Reg()
DataMirror.isVisible
and other things checking visibility now work properly for views.SRAMInterface
address width (backport #3830) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3840)rm -rf
java.lang.UnsatisfiedLinkError: Error looking up function 'stat': java: undefined symbol: stat
mikepenz/release-changelog-builder-action
to v4.1.1import chisel3._
import chisel3.util._
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0...v6.1.0
Published by jackkoenig 8 months ago
implicitClock
and implicitReset
that can be overridden within Module
to change what values are used as the implicit clock and implicit reset respectively.SRAMInterface
parameters publicly available (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3826)memSize
, dataType
, numReadPorts
, numWritePorts
, numReadwritePorts
, masked
parameters are now visible for SRAMInterface
.--use-legacy-shift-right-width
. Users are encouraged to generate Verilog with and without this option and diff it to ensure the width change does not affect the correctness of their design. Note that this option is purely for code migration and should not be used long term--it will eventually be removed.%
.Reg()
to properly handle clocks as rvalues (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3775)
DataView
(including FlatIO
)Reg()
DataMirror.isVisible
and other things checking visibility now work properly for views.SRAMInterface
address width (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3830)rm -rf
java.lang.UnsatisfiedLinkError: Error looking up function 'stat': java: undefined symbol: stat
mikepenz/release-changelog-builder-action
to v4.1.1import chisel3._
import chisel3.util._
mlirBytecodeStream
to PanamaCIRCT
(by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3823)Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0...v7.0.0-M1
Published by jackkoenig 9 months ago
ConstType
and Const(...)
API (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3046)Const()
API to create ConstType
s, which denotes Data
that holds a constant value.SyncReadMem.readWrite(address, writeData, enabled, isWrite)
explicitly generates a read-write port that supports both read and write access to the memory.skipPrefix
to enable ignoring the last prefix value in the prefix name stack.circt.clock_gate
intrinsic..unsafe
, a useful function on Connectable when users want a connection to "try its best but don't error"..squeezeAllAs
, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired..as
, a useful function on Connectable when users to upcast the Scala type..reset
svsim.Backend
implementations outside of Chisel. This is useful since in-tree backends may not support all versions of the specified backend (and we don't necessarily want them to).CHISEL_USE_COLOR
. Set to true
to force Chisel to use color and false
to disable it.TERM
to be set to something other than dumb
.SyncReadMem
wrapper is instantiated using a new object, SRAM.apply
, and invokes .write
, .read
, and .readWrite
to generate a desired number of read, write, and read/write ports. This function returns a new Bundle
wire containing the control signals for each requested port.errorOnAsUInt
to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.SRAM.apply
and SRAM.masked
now take a contents
parameter, by default a None
, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.SRAM
APIs that take three Clock
sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock
sequence and drive them accordingly.take
method on Bits
that returns the requested number (by @chick in https://github.com/chipsalliance/chisel/pull/3402)take
will accept an argument of zero and will return a zero-length UIntFirtoolBinaryPathOption
to select a different firtool
binary at runtime.Data
and can only be used by simulation-only APIs.AnyRef
type and rework PropertyType.getPropertyType
(by @albertchen-sifive in https://github.com/chipsalliance/chisel/pull/3522)aliasName
to Bundles: a way for users to define a type alias for a bundle type, resulting in the emission and usage of alias type statements in FIRRTL.HasAutoTypename
trait
typeName
for Bundle
objects through the compiler plugin.DedupGroupAnnotation
phase that generates deduplication groups based on module desiredNames
:=
connects for probes, which will emit a ProbeDefine.disallowIOCreation()
. This is useful for building chisel libraries which desire this behavior, but don't want to force a user to declare the entire IO in one bundle.@instantiable
and @pulic
.dontTouch
will maintain the same behavior by default by applying dontTouch
to every leaf when the argument is an Aggregate. The new argument markAgg
can be set to true
to have dontTouch
mark the Aggregate instead.SRAM
targets accessible from SRAMInterface
s instantiated via the SRAM
object, which sets the underlying
field in SRAMInterface
.rwTap
) API to BoringUtils, which drills writable probe ports downwards only.clock
and cond
from probe force
and release
methods.MemoryWritePort
and MemoryReadWritePort
classes publicly accessible.CHISEL_FIRTOOL_PATH
is set, it will check forCHISEL_FIRTOOL_CACHE
environment variable.trait AutoCloneType
(its always enabled, the trait is a no-op)chisel3.experimental.ChiselEnum
(use chisel3.ChiselEnum
)chisel3.experimental.EnumType
(use chisel3.EnumType
)chisel3.experimental.EnumType
(use chisel3.reflect.DataMirror
)chisel3.internal.requireIsHardware
(use chisel3.experimental.requireIsHardware
)chisel3.internal.requireIsChiselType
(use chisel3.experimental.requireIsChiselType
)chisel3.internal.sourceinfo.*
(use chisel3.experimental.sourceinfo.*
)chisel3.internal.prefix
(use chisel3.experimental.prefix
)chisel3.internal.noPrefix
(use chisel3.experimental.noPrefix
)chisel3.internal.ChiselException
(use chisel3.ChiselException
)chisel3.internal.InstanceId
(use chisel3.InstanceId
)trait BackendCompilationUtilities
chisel3.util.MuxLookup(key, default, mapping)
(use chisel3.util.MuxLookup(key, default)(mapping)
, it has much better type inferencing behavior)BoringUtils.bore(source, sinks)
, BoringUtils.addSource
and BoringUtils.addSink
are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source)
, BoringUtils.tap(source)
...val x = (Wire(Bool()), Wire(Bool()))
will generate wires with names x_1
and x_2
const
wires. This will facilitate further support for const
in operations and the type system in the future.assert
from an svsim
simulation run may kill the simulated process before it can finish writing a waveform.SyncReadMem.readWrite
when explicit clocks are used (by @jared-barocsi in https://github.com/chipsalliance/chisel/pull/3313)stderr
could hangprobe.force
and probe.forceInitial
methods. (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3418)probe.force
and probe.forceInitial
methods. Error out on unknown widths.:
between filename and line number).chirrtl.memoryport
position (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3544)simpleClassName
utility object that emulates a getClass.getSimpleName
call without throwing Malformed class name
exceptions when Java 8 is used. typeName
and all related implementations use this function now instead of getClass.getSimpleName
.HasAutoTypename
can no longer be mixed into an anonymous Record
; the compiler plugin now reports this as a compilation error.foo
and then foo_
will no longer trigger an error.Vec
s, also set the probeInfo
of their sample_element
, which is used to determine its element type.--mlir-print-ir-after-all
option. (by @poemonsense in https://github.com/chipsalliance/chisel/pull/3704)--mlir-print-ir-after-all
option.[docs] Fix README logo and update versions (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3189)
[fix] typo fix: chosen port of arbiter is not onehot but UInt (by @SihaoLiu in https://github.com/chipsalliance/chisel/pull/3235)
Just a oneline fix to the comment of Arbiter chosen port
[docs] Update website for 5.0, 6.0 and fix links (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3274)
Update roadmap. (by @gonsolo in https://github.com/chipsalliance/chisel/pull/3295)
Bring ToC and Menu into alignment, some minor cleanup within docs (by @mwachs5 in https://github.com/chipsalliance/chisel/pull/3346)
Fix https://github.com/chipsalliance/chisel/issues/3322
Remove references to interval types from the website docs (by @mwachs5 in https://github.com/chipsalliance/chisel/pull/3345)
Fixes https://github.com/chipsalliance/chisel/issues/3325
Update meeting time and versions in README (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3356)
README.md: Fix link to gitter badge (by @smarter in https://github.com/chipsalliance/chisel/pull/3370)
Add Chips Alliance to README (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3377)
Update suggested milestones in PULL_REQUEST_TEMPLATE.md (by @mwachs5 in https://github.com/chipsalliance/chisel/pull/3394)
Update the PULL REQUEST TEMPLATE to prompt for 6.0 and 5.0.x milestones
Update versioning.md for Chisel 5.0.0. (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3421)
Describe new use of SemVer and update older text that applies to only Chisel 3.0-3.6.
[docs] Fix chiseltest version in old compatible versions (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3448)
[docs] Update naming explanation for newer firtool (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3454)
[website] Fix link from Warnings to Cookbook (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3524)
Fix HasTypeAlias cookbook typos (by @jared-barocsi in https://github.com/chipsalliance/chisel/pull/3525)
Add unit test demonstrating BoringUtils.tap with D/I (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3540)
Changed Array to Seq in MuxLookup explantation (by @madsrumlenordstrom in https://github.com/chipsalliance/chisel/pull/3547)
[docs] Switch API docs hosting from javadoc.io to sonatype (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3568)
[ci] Record published version in step summary (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3645)
[docs] Migrate website to Docusaurus (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3646)
Introducing a complete facelift of the Chisel website, now built with Docusaurus 3.0.
Better reference to the Chisel book. (by @schoeberl in https://github.com/chipsalliance/chisel/pull/3649)
[website] Add robots.txt (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3650)
This will hopefully make the Algolia web crawler work.
[website] Docusaurus set trailingSlash to false (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3653)
[website] Enable Algolia-powered search (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3651)
[website] docs/introduction => docs/index, add redirects (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3656)
[website] More redirects (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3657)
Redirect links with .html
or .htm
(remove the extension). Do this same redirect for old website /chisel3/...
links as well.
[docs] Update README after 5.1.0 release (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3660)
[website] Generate links to ScalaDoc for API page (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3661)
The website will now actual reflect the latest snapshot and releases on the API page
[website] Self-host latest [stable] API docs (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3665)
This should enable them to be indexed and thus searchable as part of the website (both by Algolia and by Google).
Fix spelling error in Layers documentation layers.md (by @t14916 in https://github.com/chipsalliance/chisel/pull/3673)
[docs] Fix release ordering and make RC count as latest (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3686)
[docs] update firtool version (by @schoeberl in https://github.com/chipsalliance/chisel/pull/3670)
[docs] Add Firtool versions table to Versioning page (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3694)
This table is generated for all versions of Chisel that include BuildInfo.firtoolVersion
and will thus automatically include new releases. Versions of Chisel that predate BuildInfo.firtoolVersion
are included in the table manually.
[docs] Fix links from ScalaDoc to source code (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3697)
Add riscvassembler lib to community projects (by @carlosedp in https://github.com/chipsalliance/chisel/pull/3717)
Added RISCVAssembler Scala library to community projects.
[CI] Make SBT version handling logic more robust (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3738)
<unknown>
.CHISEL_FIRTOOL_PATH
.project/previous-versions.txt
on relevant release branches. build.sbt
also now contains instructions are how to waive binary compatibility breakages.ChiselRunner
tests now use svsim
when calling assertTester{Passes,Fails}
CHISEL_ARGUMENT_EXTENSIONS
environment variable is set to DISABLE
PanamaCIRCTConverter
(by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3520)collectAlignedDeep
) no longer require Data to be Hardware and may be used on bare Chisel types.Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.1.0...v6.0.0
Published by jackkoenig 9 months ago
SRAM
targets accessible from SRAMInterface
s instantiated via the SRAM
object, which sets the underlying
field in SRAMInterface
.trait AutoCloneType
(its always enabled, the trait is a no-op)chisel3.experimental.ChiselEnum
(use chisel3.ChiselEnum
)chisel3.experimental.EnumType
(use chisel3.EnumType
)chisel3.experimental.EnumType
(use chisel3.reflect.DataMirror
)chisel3.internal.requireIsHardware
(use chisel3.experimental.requireIsHardware
)chisel3.internal.requireIsChiselType
(use chisel3.experimental.requireIsChiselType
)chisel3.internal.sourceinfo.*
(use chisel3.experimental.sourceinfo.*
)chisel3.internal.prefix
(use chisel3.experimental.prefix
)chisel3.internal.noPrefix
(use chisel3.experimental.noPrefix
)chisel3.internal.ChiselException
(use chisel3.ChiselException
)chisel3.internal.InstanceId
(use chisel3.InstanceId
)trait BackendCompilationUtilities
chisel3.util.MuxLookup(key, default, mapping)
(use chisel3.util.MuxLookup(key, default)(mapping)
, it has much better type inferencing behavior)--mlir-print-ir-after-all
option. (by @poemonsense in https://github.com/chipsalliance/chisel/pull/3704)--mlir-print-ir-after-all
option.BuildInfo.firtoolVersion
and will thus automatically include new releases. Versions of Chisel that predate BuildInfo.firtoolVersion
are included in the table manually.<unknown>
.CHISEL_FIRTOOL_PATH
.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-RC1...v6.0.0-RC2
Published by jackkoenig 10 months ago
AnyRef
type and rework PropertyType.getPropertyType
(by @albertchen-sifive in https://github.com/chipsalliance/chisel/pull/3522)aliasName
to Bundles: a way for users to define a type alias for a bundle type, resulting in the emission and usage of alias type statements in FIRRTL.HasAutoTypename
traittypeName
for Bundle
objects through the compiler plugin.DedupGroupAnnotation
phase that generates deduplication groups based on module desiredNames
:=
connects for probes, which will emit a ProbeDefine.disallowIOCreation()
. This is useful for building chisel libraries which desire this behavior, but don't want to force a user to declare the entire IO in one bundle.@instantiable
and @pulic
.dontTouch
will maintain the same behavior by default by applying dontTouch
to every leaf when the argument is an Aggregate. The new argument markAgg
can be set to true
to have dontTouch
mark the Aggregate instead.clock
and cond
from probe force
and release
methods.MemoryWritePort
and MemoryReadWritePort
classes publicly accessible.const
wires. This will facilitate further support for const
in operations and the type system in the future.chirrtl.memoryport
position (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3544)simpleClassName
utility object that emulates a getClass.getSimpleName
call without throwing Malformed class name
exceptions when Java 8 is used. typeName
and all related implementations use this function now instead of getClass.getSimpleName
.HasAutoTypename
can no longer be mixed into an anonymous Record
; the compiler plugin now reports this as a compilation error.foo
and then foo_
will no longer trigger an error.Vec
s, also set the probeInfo
of their sample_element
, which is used to determine its element type..html
or .htm
(remove the extension). Do this same redirect for old website /chisel3/...
links as well.PanamaCIRCTConverter
(by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3520)collectAlignedDeep
) no longer require Data to be Hardware and may be used on bare Chisel types.Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M3...v6.0.0-RC1
Published by jackkoenig 11 months ago
CHISEL_USE_COLOR
. Set to true
to force Chisel to use color and false
to disable it.TERM
to be set to something other than dumb
.SyncReadMem
wrapper is instantiated using a new object, SRAM.apply
, and invokes .write
, .read
, and .readWrite
to generate a desired number of read, write, and read/write ports. This function returns a new Bundle
wire containing the control signals for each requested port.SRAM.apply
and SRAM.masked
now take a contents
parameter, by default a None
, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.SRAM
APIs that take three Clock
sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock
sequence and drive them accordingly.SyncReadMem.readWrite
when explicit clocks are used (backport #3313) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3316)assert
from an svsim
simulation run may kill the simulated process before it can finish writing a waveform.stderr
could hangFull Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0...v5.1.0
Published by jackkoenig about 1 year ago
errorOnAsUInt
to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.SRAM.apply
and SRAM.masked
now take a contents
parameter, by default a None
, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.SRAM
APIs that take three Clock
sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock
sequence and drive them accordingly.take
method on Bits
that returns the requested number (by @chick in https://github.com/chipsalliance/chisel/pull/3402)take
will accept an argument of zero and will return a zero-length UIntFirtoolBinaryPathOption
to select a different firtool
binary at runtime.Data
and can only be used by simulation-only APIs.BoringUtils.bore(source, sinks)
, BoringUtils.addSource
and BoringUtils.addSink
are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source)
, BoringUtils.tap(source)
...val x = (Wire(Bool()), Wire(Bool()))
will generate wires with names x_1
and x_2
stderr
could hangprobe.force
and probe.forceInitial
methods. (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3418)probe.force
and probe.forceInitial
methods. Error out on unknown widths.:
between filename and line number).CHISEL_ARGUMENT_EXTENSIONS
environment variable is set to DISABLE
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M2...v6.0.0-M3
Published by jackkoenig over 1 year ago
.reset
svsim.Backend
implementations outside of Chisel. This is useful since in-tree backends may not support all versions of the specified backend (and we don't necessarily want them to).CHISEL_USE_COLOR
. Set to true
to force Chisel to use color and false
to disable it.TERM
to be set to something other than dumb
.SyncReadMem
wrapper is instantiated using a new object, SRAM.apply
, and invokes .write
, .read
, and .readWrite
to generate a desired number of read, write, and read/write ports. This function returns a new Bundle
wire containing the control signals for each requested port.rwTap
) API to BoringUtils, which drills writable probe ports downwards only.assert
from an svsim
simulation run may kill the simulated process before it can finish writing a waveform.SyncReadMem.readWrite
when explicit clocks are used (by @jared-barocsi in https://github.com/chipsalliance/chisel/pull/3313)ChiselRunner
tests now use svsim
when calling assertTester{Passes,Fails}
Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M1...v6.0.0-M2
Published by jackkoenig over 1 year ago
chisel3.util.MuxLookup.fromEnum
.fir
. Now emitting FIRRTL version 1.2.0.MuxLookup.apply
that takes two parameter lists instead of one. This helps the scala compiler report better type errors.svsim
, a low level library for simulating SystemVerilog using Verilator and VCS. (by @GeorgeLyon in https://github.com/chipsalliance/chisel/pull/3121)svsim
, a new library for compiling and controlling SystemVerilog simulations in Scala using Verilator or VCS.Simulator
class for simulating Chisel modules with svsim
(by @GeorgeLyon in https://github.com/chipsalliance/chisel/pull/3136)
chisel3.simulator.Simulator
for simulating Chisel modules with svsim
chisel3.simulator.EphemeralSimulator
for ephemeral scenarios (such as scala-cli)Modules
and Queues
.exclude
mechanism on Connectable
to enable never connecting to/from the marked fields using any connectable operator.VecInit.fill(0)
calls so that they compile and yield 0-width Vecs
SyncReadMem.readWrite(address, writeData, enabled, isWrite)
explicitly generates a read-write port that supports both read and write access to the memory..unsafe
, a useful function on Connectable when users want a connection to "try its best but don't error"..squeezeAllAs
, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired..as
, a useful function on Connectable when users to upcast the Scala type..reset
Chisel
and the NotStrict
compile options.Module
or BlackBox
..fir
file instead of in an auxiliary .anno.json
file.gcc
versions (by @GeorgeLyon in https://github.com/chipsalliance/chisel/pull/3132)firrtl
, chisel3-macros
, chisel3-core
, and chisel3
artifacts into a single artifact: chisel
.git describe --tag
. SNAPSHOTs will now be unique per push to main.project/previous-versions.txt
on relevant release branches. build.sbt
also now contains instructions are how to waive binary compatibility breakages.Full Changelog: https://github.com/chipsalliance/chisel/compare/a005498...v5.0.0
Published by jackkoenig over 1 year ago
ConstType
and Const(...)
API (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3046)Const()
API to create ConstType
s, which denotes Data
that holds a constant value.SyncReadMem.readWrite(address, writeData, enabled, isWrite)
explicitly generates a read-write port that supports both read and write access to the memory.skipPrefix
to enable ignoring the last prefix value in the prefix name stack.circt.clock_gate
intrinsic..unsafe
, a useful function on Connectable when users want a connection to "try its best but don't error"..squeezeAllAs
, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired..as
, a useful function on Connectable when users to upcast the Scala type.project/previous-versions.txt
on relevant release branches. build.sbt
also now contains instructions are how to waive binary compatibility breakages.Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-RC2...v6.0.0-M1
Published by jackkoenig over 1 year ago
SyncReadMem.readWrite(address, writeData, enabled, isWrite)
explicitly generates a read-write port that supports both read and write access to the memory..unsafe
, a useful function on Connectable when users want a connection to "try its best but don't error"..squeezeAllAs
, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired..as
, a useful function on Connectable when users to upcast the Scala type.project/previous-versions.txt
on relevant release branches. build.sbt
also now contains instructions are how to waive binary compatibility breakages.Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-RC1...v5.0.0-RC2
Published by jackkoenig over 1 year ago
chisel3.simulator.EphemeralSimulator
for ephemeral scenarios (such as scala-cli)Modules
and Queues
.exclude
mechanism on Connectable
to enable never connecting to/from the marked fields using any connectable operator.VecInit.fill(0)
calls so that they compile and yield 0-width Vecs
.fir
file instead of in an auxiliary .anno.json
file.Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-M2...v5.0.0-RC1