chisel

Bump FIRRTL version.

Bump FIRRTL version to 1.1.5

This version bumps the firrtl dependency to 1.1.4 and adds the following features and bug fixes:

• Bump scopt from 3.6.0 -> 3.7.0 (#877)
• Update description given that Chisel3 has been released (#948)
• Make Vec cloneType keep directions of elements (#945)
• Add Chisel logo to README (#935)
• Add SVG and PNG formatted Chisel logos (#930)
• Fix Queue.io.count when entries=1 (#918)
• Check BaseModule.name for NullPointerException (#912)
• Modify ReadyValidIO noenq to set the data payload to DontCare. (#902)
• Add CODEOWNERS file (#895)
• Documentation tweaks (#894)
• Support for verilog memory loading. (#840)

This release includes the following bug fixes and features and updates dependency versions:

• Update versions and links in README (#855)
• Cleanup implicit conversions (#868)
• Minor tweaks to the style guide (#876)
• MixedVec implementation. (#850)

This release contains bug fixes and updates the expected FIRRTL version.

• Add support for Input() and Output() (available in Chisel2 since ucb-bar/chisel2-deprecated#734) and test for same. (#862)
• Correcting documentation errors in Arbiter.scala (#839)
• Add Emacs temporaries, backups to .gitignore (#837)
• Catch returns from within when blocks and provide an error message (#842)
• Ignore eclipse temporaries (#843)
• Undeprecate log2Up and log2Down (#846)

• Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778)
• Suggest wrapping in Wire() or IO() in requireIsHardware (#827)
• Use Vec.apply instead of new Vec in VecInit.apply (#825)
• Remove extraneous traversal in cloneSupertype (#824)
• Fix UIntToOH for output widths larger than 2^(input width) (#823)
• Add test for zero-width Mems. (#821)
• Minor edits to wording in ErrorLog.checkpoint() for deprecations. (#817)
• Make Mem and SyncReadMem constructors private (#816)
• Add Module.currentModule for getting a reference to the current Module (#810)

This release incorporates changes from v3.1.0-RC1 and v3.1.0-RC2. Please see the release notes from those candidates.

This release candidate contains a Style Guide (curtesy of Kevin Townsend) and the following bug fixes:

• Fallback null insertion for autoclonetype (#801)
  If autoclonetype is unable to determine an outer class, this attempts to insert a null (and give a deprecation warning), preserving old behavior (in some cases) where the new behavior doesn't work.
• Fix SyncReadMem.read; add test (#796)
  SyncReadMem.read with an enable signal currently only works in compatibility mode, where Wires are implicitly initialized to DontCare. Fix by explicitly assigning DontCare to the Wire.
• Stricter updateBundleStack - addresses #792 (#793)

This release contains the following backward incompatible API changes:

• Refactor Annotations (#767)

If you are using your own build and execution harness that does not use one of the Driver.execute family, you may need to explicitly load annotations into memory and then set the annotations field of the optionsManager.firrtlOptions. For an example, see lines 124-125 of chisel-testers/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala.

This release includes the following bug and typo fixes:

• Fix deprecations in tests (#762)
• Update README.md with release status and supported Verilator version. (#759)
• Fixes format strings in assertions. Fixes #540 (#542)
• Remove (possibly) extraneous aggregate() line. (#748)

This release includes the following new features:

• Performance problems with sbt 1.0.4
  • Add companion objects to macro classes (#787)
• Support zero-entry queues (but not for irrevocable) (#780)
• Make Bundle abstract (#774)
• Bump sbt to 1.1.1 (#773)
• Runtime API deprecation warnings (#761)
• Significant changes to support the ability to auto clone more data types (#723)
  • Auto Clone Bundles in Companion Objects (#788)
  • Support for inner classes, implicit parameter lists, supertypess
  • Add support for autoclonetype of bound, anonymous inner Bundles (#722)
  • Make uncloneable IO deprecated instead of error, improve error handling (#771)
  • Cloning IO with compatibility (#754)
  • Better support for autoclonetype of nested Bundles (#769)
  • Autoclonetype will clone args that are of type data (#768)
  • Change clonetype test to be autoclonetype friendly (#757)

This release of chisel uses version 1.0.2 of firrtl

• The register creation API has been changed to offer clearer functional choices. (#553)
  • RegInit should be used to create a register with a specified initializer.
  • RegNext should be used to create a register with a specified next value.
• log2Up and log2Down have been deprecated, users should now use log2Ceil and log2Floor. Internal references to these functions have been fixed.. (#528)
• QueueIO and ArbiterIO work proper when given zero entries.
• Support has been added for field names that begin with a number in the new aggregate type Record. (#531)
• New warnings on inappropriate parameters for a number of chisel constructs. (#455)
  • Vec creation warns when type given is a literal. (#530)
• If OHToUInt is given only one argument it always returns that. (#546)
• Custom transforms are executed in the order they are specified in the options manager. (#532)
• ShiftRegister applies the enable to all registers created. (#370)
• Fixed a bug where compile errors were caused by assertions containing %. (#500)
• Fixed an an inconsistency in Chisel, a UInt -& UInt now returns an SInt. (#502)
• There is a new low level API for creating elements of a given type asTypeOf. (#450)
  • fromBits currently untouched but will be chisel3-deprecated if possible as a future PR.
  • Code that needs to create a super-type of several types into cloneSupertype See. #446
    • This should be the only thing that changes externally visible API, in that the checks are now more consistent.
    • oneHotMux now checks against inconsistent input types.
    • Mux now checks that each branch is of equivalent type.
  • Simplify Vec construction using above.
  • Move cloneTypeWidth from Data to Bits. It used to silently drop the width parameter when called on any non-Bits, this makes uses of it explicit and always correct, minus the Bool case.
  • Eventually want to get rid of cloneTypeWidth. The only stragglers are Bits.pad (which can instead create a new UInt/etc from scratch) and Reg (which clears widths behind the scenes for you). Not sure how to address the Reg case.
• Deprecate flatten, hopefully will remove it eventually using more local operations.

• Use input element to decide if Vec of values has direction. (#570)
• Define CompileOptions case class to support CompileOptions manipulation. (#572)
• Make Module instantiations draw clock from Builder instead of parent (#568)
• Creating FixedPoint literals was throwing away width when specifically provided. This caused one hot muxing problems in dsptools FixedPoint spec fixed based on error uncovered by this change. (#564)
• Support Vec(0) fields in Bundles, just like Option[Data]; add test (#562)
• Fix getWidth on empty Vecs; add test (#561)
• Fixed fix, allow Mux of different binary points and widths (#559)

• Update instructions for installing firrtl. (#597)
• Deprecate fromBits and clock/reset constructors (#583)
• Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)
• Remove explicit import of NotStrict - fixes #492 (#494)
• Remove VecLike/IndexedSeq from Mem type (#589)
• Fix assignment from 0-entry Vec: add test (#580)
• Fix macOS install instructions for homebrew package manager (#575)
• Module Hierarchy Refactor (#469)
• Fix one hot mux (#573)
• Change Enum to emit minimum widths of 1 (#574)

• Changed multiplication of SInt and UInt (#611)
• Scope resources - move them down into chisel3 directory - fixes #549 (#610)
• Add implicit CompileOptions to Record and Bundle (#595)
• Connecting basic types wrong should error in chisel (#497)
• Clear clock and reset scope for RawModule (#607)

• Update internal Pipe wiring - fixes #615 (#616)

• Correct misleading example code
• Support updated scalatest/scalacheck; bump sbt and Scala versions. (#605)
• Update comments describing Decoupled/ReadyValid - fix #437. (#493)

• Fix a small typo in the README (#627)
• Add dontTouch for annotating Data to not be removed (#620)
• Don't try to instantiate firrtl.Transform from Annotation (#620)

• Update deprecated code in build.sbt (#648)
• Ensure IO is non-null before attempting to autoWrapPorts. (#643)
• Fix syntax of README.md (#641)
• Directions internals mega-refactor (#617)

• Make .dir give correct direction for Module io in compatibility (#673)
• Rename userDir->specifiedDir (#671)
• README: Java package (#670)
• Give default direction to children of Vecs in compatibility code (#667)
• Don't assign default direction to Analog in Chisel._ (#664)
• Address scalastyle issues, out of date comments, extraneous imports. (#658)
• Black box top-level IO fix (#655)
• Add rebinding test (#654)
• Fix style of literal creators (#637)
• Simplify macOS install instructions (#599)
• Fixed point width inference was wrong when binary points didn't align. (#590)

This is the first Chisel3 BIG4 SNAPSHOT release to support Scala 2.12.
Unfortunately, behavior we've come to rely on when generating anonymous classes structurally has been deemed a bug in Scala 2.12 ("Inferred types for fields").
This is Chisel3 issue (#606).

The following code:

import Chisel._

class MyModule extends Module {
  val io = new Bundle {
    val in = UInt(INPUT, width = 8)
    val out = UInt(OUTPUT, width = 8)
  }
  io.out := io.in
}

Results in:

Error:(12, 6) value out is not a member of Chisel.Bundle
  io.out := io.in
Error:(12, 16) value in is not a member of Chisel.Bundle
  io.out := io.in

NOTE: This seems to be constrained to compatibility mode.
The normal chisel3 wrappers IO(), Wire() cause the inferred value to be the structural type of their argument (the behavior we desire).
As stated in Chisel3 issue (#606), the work around is to add:

scalacOptions ++= Seq("-Xsource:2.11")

to your build.sbt file if you're using Chisel3 in compatibility mode with Scala 2.12.

• Update sbt to 0.13.16; add Scala 2.12 support.(#675)
• Added API to get Verilog from Chisel (#676)
• Update README (#683)
• Use firrtl elses in elsewhen/otherwise case emission (#510)
• More of the bindings refactor (#635)
• Make Reset a trait (#672)