chisel

Chisel: A Modern Hardware Design Language

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chisel - Chisel v6.5.0 Latest Release

Published by jackkoenig 3 months ago

Features

API Deprecation

Performance

Fixes

Documentation

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.4.0...v6.5.0

chisel - Chisel v7.0.0-M2

Published by jackkoenig 3 months ago

Features

API Modification

  • Fix tests to avoid inferred width ports on public modules. (by @dtzSiFive in https://github.com/chipsalliance/chisel/pull/3869)
    Main module are "public" (#3813, soon mandatory) which means they cannot have inferred widths or abstract resets. Code relying on old behavior will presently encounter an error in firtool.
  • Remove circt.Intrinsic annotation. (by @dtzSiFive in https://github.com/chipsalliance/chisel/pull/3945)
    IntrinsicModules (intmodule's in FIRRTL) have replaced this entirely for some time now.
  • [svsim] Expose further verilator options for trace file name and simulation speed optimization (by @kammoh in https://github.com/chipsalliance/chisel/pull/3985)
  • Make AssertPropertyLike.createIntrinsic protected (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/4058)
    It should never have been a public API
  • checkTypeEquivalence now considers ProbeInfo (by @mwachs5 in https://github.com/chipsalliance/chisel/pull/4064)
    Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).
  • Make "deprecated public" binding APIs private (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/4177)
    These chisel3.internal APIs should never have been public in the first place.
  • Fix width of ChiselEnum values in emitted FIRRTL (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/4200)
    Fixes https://github.com/chipsalliance/chisel/issues/4159.
    Previously, the width reported by Chisel under .getWidth was inconsistent with the width of the emitted FIRRTL for ChiselEnum values cast to UInt.
    Temporarily preserve the old behavior under CLI option --use-legacy-width (formerly known as --use-legacy-shift-right-width). Users are encouraged to build Verilog with and without this option enabled and diff the result to verify that this change in width behavior did not silently affect the correctness of their designs.
  • Preserve literals across .asTypeOf (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/4168)
    Casting a literal (of any type) to another type with .asTypeOf will result in a literal of the new type. For non-literals, the FIRRTL representation will now be a little bit more efficient.
  • Intern Width (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/4242)
    • UnknownWidth becomes a case object (Drop () when using it).
    • KnownWidths 0-1024 are interned
  • SourceInfo: simplify the common case for makeMessage, print it differently (by @mwachs5 in https://github.com/chipsalliance/chisel/pull/4249)
    Add a default to SourceInfo.makeMessage() so that users don't always have to write makeMessage(x => x). Change the toString of SourceLine so that it puts a colon instead of a space between the file name and line number, which makes it possible to click-to-source in editors like VSCode.
  • Micro-optimize Direction (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/4251)
    • Specified and actual direction information are each now stored as single bytes rather than references.
    • This reduces the memory use of a typical bound UInt from 72 bytes shallow, 128 bytes retained to 64 bytes shallow, 120 bytes retained.
    • The change is mostly source compatible, but ActualDirection.Bidirectional, has changed slightly to memoize its two possibilities (Bidirectional.Default and Bidirectional.Flipped). There are deprecations for the typical APIs

API Deprecation

Backend Code Generation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v7.0.0-M1...v7.0.0-M2

chisel - Chisel v3.6.1

Published by jackkoenig 4 months ago

Features

  • Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3213)
  • Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #3181) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3258)
  • Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3335)
    • Chisel will now detect when it should print warnings, errors, and deprecations in color.
      • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
      • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
  • Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3361)
    This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
  • SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3379)
    SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
  • Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3390)
  • SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3404)
    Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
  • Add Instance.suggestName (backport #2886) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3723)
    Adds suggestName API for hierarchy instances.
  • Implement typeName API for stable Module names (backport #3130) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/4145)
    This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues

API Deprecation

Backend Code Generation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v3.6.0...v3.6.1

chisel - Chisel v6.4.0

Published by jackkoenig 5 months ago

Features

API Modification

  • checkTypeEquivalence now considers ProbeInfo (backport #4064) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/4112)
    Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).

API Deprecation

Fixes

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.3.0...v6.4.0

chisel - Chisel v5.3.0

Published by jackkoenig 5 months ago

Fixes

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.2.0...v5.3.0

chisel - Chisel v6.3.0

Published by jackkoenig 6 months ago

Features

  • Add DeletedPath for targets that no longer exist. (backport #3937) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3938)
    Sometimes a generator wants to emit a Path that targets some Data, but that Data isn't always produced by the generator. The DeletedPath can be used to represent the presence of a Path, but the absence of a Data in this case.
  • Add requireIsAnnotatable for better errors when annotating literals (backport #3968) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3971)
    This gives much better error messages when accidentally dontTouching a literal

Performance

Fixes

Documentation

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.2.0...v6.3.0

chisel - Chisel v5.2.0

Published by jackkoenig 6 months ago

Features

Backend Code Generation

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.1.0...v5.2.0

chisel - Chisel v6.2.0

Published by jackkoenig 8 months ago

Features

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.1.0...v6.2.0

chisel - Chisel v6.1.0

Published by jackkoenig 8 months ago

Features

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0...v6.1.0

chisel - Chisel v7.0.0-M1

Published by jackkoenig 8 months ago

Features

API Modification

  • Refactor panama binding and converter framwork (by @sequencer in https://github.com/chipsalliance/chisel/pull/3754)
  • Change the width of static shift right (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3824)
    • A UInt shifted right by a static amount >= its width will now result
      in a 0-bit UInt
    • An SInt shifted right by a static amount >= its width will now result
      in a 1-bit SInt (the sign bit)
      This is a change for SInts which Chisel would treat the output as a 0-bit SInt. However, FIRRTL implemented different behavior where both UInts and SInts would result in 1-bit values (which shifted right by an amount >= the width of the input).
      Users can emulate the old behavior by providing CLI option --use-legacy-shift-right-width. Users are encouraged to generate Verilog with and without this option and diff it to ensure the width change does not affect the correctness of their design. Note that this option is purely for code migration and should not be used long term--it will eventually be removed.
  • Bump to firtool-resolver 2.0.0 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3855)
    This change should be non-breaking for the vast majority of users; however, it does have a substantial impact on Chisel's transitive dependencies which could affect some users. The following transitive dependencies were dropped:
    • com.github.luben:zstd-jni:1.5.5-10
    • com.github.plokhotnyuk.jsoniter-scala::jsoniter-scala-core:2.13.5.2
    • com.lihaoyi::sourcecode:0.3.1
    • com.outr::moduload:1.1.7
    • com.outr::perfolation:1.2.9
    • com.outr::scribe:3.13.0
    • commons-io:commons-io:2.15.0
    • io.get-coursier.jniutils:windows-jni-utils:0.3.3
    • io.get-coursier::coursier-cache:2.1.8
    • io.get-coursier::coursier-core:2.1.8
    • io.get-coursier::coursier-proxy-setup:2.1.8
    • io.get-coursier::coursier-util:2.1.8
    • io.get-coursier::coursier:2.1.8
    • io.github.alexarchambault.windows-ansi:windows-ansi:0.0.5
    • io.github.alexarchambault:concurrent-reference-hash-map:1.1.0
    • javax.inject:javax.inject:1
    • org.apache.commons:commons-compress:1.24.0
    • org.apache.xbean:xbean-reflect:3.7
    • org.codehaus.plexus:plexus-archiver:4.9.0
    • org.codehaus.plexus:plexus-classworlds:2.6.0
    • org.codehaus.plexus:plexus-container-default:2.1.1
    • org.codehaus.plexus:plexus-io:3.4.1
    • org.codehaus.plexus:plexus-utils:4.0.0
    • org.fusesource.jansi:jansi:1.18
    • org.iq80.snappy:snappy:0.4
    • org.slf4j:slf4j-api:1.7.36
    • org.tukaani:xz:1.9
    • org.virtuslab.scala-cli::config:0.2.1
      Any users experiencing issues should consider manually adding whichever of these dependencies they may be relying on.

Backend Code Generation

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0...v7.0.0-M1

chisel - Chisel v6.0.0

Published by jackkoenig 9 months ago

Features

API Modification

  • Create "tap" API for boring probe-type (non-synthesizable) ports (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3237)
    Create "tap" API for boring probe-type (non-synthesizable) ports.
  • BoringUtils writable tap (rwTap) API (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3284)
    Add writable tap (rwTap) API to BoringUtils, which drills writable probe ports downwards only.
  • Remove support for Scala 2.12 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3331)
    Chisel 5 was the last major version supporting Scala 2.12, please upgrade to Scala 2.13.
  • Error when calling .viewAs on non-hardware (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3398)
  • Add a new BaseType type that Data inherits, and use it for ports. (by @mikeurbach in https://github.com/chipsalliance/chisel/pull/3429)
  • Make LTL properties use Clock and Disable by default (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3498)
    Properties in package chisel3.ltl will now be clocked and disabled by default (if there is an implicit clock and disable). Default disable is not hasBeenReset of the current implicit reset (if one exists). The clock and disable can be removed by setting them to None via withClock, withReset, and withDisable APIs.
  • Property now extends Data, remove BaseType (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3514)
    Properties can be fields of Bundles and used in wires.
  • MixedVec subclasses immutable.IndexedSeq (by @mwachs5 in https://github.com/chipsalliance/chisel/pull/3539)
    Change MixedVec to inherit from collection.immutable.IndexedSeq, so that it can work for Seq[Data].
  • remove clock and cond from probe force/release API (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3605)
    Remove clock and cond from probe force and release methods.
  • Remove Map and Tuple property types. (by @mikeurbach in https://github.com/chipsalliance/chisel/pull/3627)
    These property types weren't necessary in the end. A Map can easily be represented by a list of object with two fields, and this is how it's been done downstream. Similarly, a Tuple can easily be represented by an object with two fields, and this is how it's been done downstream. Remove these to simplify Chisel and reduce maintainence burden.
  • Rename "groups" to "layers" (by @seldridge in https://github.com/chipsalliance/chisel/pull/3632)
  • Make SRAM ports public (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3652)
    Make MemoryWritePort and MemoryReadWritePort classes publicly accessible.
  • Switch to firtool-resolver (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3458)
    Whereas in the past, the user was expected to provide the firtool binary
    on the PATH, Chisel will now manage the firtool binary automatically.
    Chisel users the following 3-step process for determining which binary
    to use:
    1. If environment variable CHISEL_FIRTOOL_PATH is set, it will check for
      firtool in that directory
    2. It will check the classpath for firtool provided by
      chipsalliance/llvm-firtool
    3. It will download a default version of chipsalliance/llvm-firtool
      Both (2) and (3) will store the firtool binary in a sensible location
      depending on the user's operating system. See dirs-dev/directories-jvm
      for more information. The user can override this location by setting the
      CHISEL_FIRTOOL_CACHE environment variable.
  • Promote FlatIO to package chisel3 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3727)
  • Make chisel3.internal.firrtl.* private (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3732)
    • Width, KnownWidth, and Unknown width promoted to package chisel3
    • Other classes moved to new package private chisel3.internal.firrtl.ir
  • Delete many old deprecated APIs (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3733)
    • trait AutoCloneType (its always enabled, the trait is a no-op)
    • chisel3.experimental.ChiselEnum (use chisel3.ChiselEnum)
    • chisel3.experimental.EnumType (use chisel3.EnumType)
    • chisel3.experimental.EnumType (use chisel3.reflect.DataMirror)
    • chisel3.internal.requireIsHardware (use chisel3.experimental.requireIsHardware)
    • chisel3.internal.requireIsChiselType (use chisel3.experimental.requireIsChiselType)
    • chisel3.internal.sourceinfo.* (use chisel3.experimental.sourceinfo.*)
    • chisel3.internal.prefix (use chisel3.experimental.prefix)
    • chisel3.internal.noPrefix (use chisel3.experimental.noPrefix)
    • chisel3.internal.ChiselException (use chisel3.ChiselException)
    • chisel3.internal.InstanceId (use chisel3.InstanceId)
    • trait BackendCompilationUtilities
    • chisel3.util.MuxLookup(key, default, mapping) (use chisel3.util.MuxLookup(key, default)(mapping), it has much better type inferencing behavior)
  • Clean up Bindings deprecations (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3736)
    • Make already deprecated APIs package private
    • Add deprecation warnings to a few that we missed

API Deprecation

Backend Code Generation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

New Contributors

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.1.0...v6.0.0

chisel - Chisel v6.0.0-RC2

Published by jackkoenig 9 months ago

Features

  • Add ModuleChoice and Groups (by @nandor in https://github.com/chipsalliance/chisel/pull/3683)
    Added support for the post-generation configuration of designs. Instance choices allow multiple, option-dependent targets to be specified for a single option, picking an implementation in the downstream flow.
  • make SRAM targets accessible from SRAMInterface (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3728)
    Makes SRAM targets accessible from SRAMInterfaces instantiated via the SRAM object, which sets the underlying field in SRAMInterface.

API Modification

  • Promote FlatIO to package chisel3 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3727)
  • Make chisel3.internal.firrtl.* private (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3732)
    • Width, KnownWidth, and Unknown width promoted to package chisel3
    • Other classes moved to new package private chisel3.internal.firrtl.ir
  • Delete many old deprecated APIs (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3733)
    • trait AutoCloneType (its always enabled, the trait is a no-op)
    • chisel3.experimental.ChiselEnum (use chisel3.ChiselEnum)
    • chisel3.experimental.EnumType (use chisel3.EnumType)
    • chisel3.experimental.EnumType (use chisel3.reflect.DataMirror)
    • chisel3.internal.requireIsHardware (use chisel3.experimental.requireIsHardware)
    • chisel3.internal.requireIsChiselType (use chisel3.experimental.requireIsChiselType)
    • chisel3.internal.sourceinfo.* (use chisel3.experimental.sourceinfo.*)
    • chisel3.internal.prefix (use chisel3.experimental.prefix)
    • chisel3.internal.noPrefix (use chisel3.experimental.noPrefix)
    • chisel3.internal.ChiselException (use chisel3.ChiselException)
    • chisel3.internal.InstanceId (use chisel3.InstanceId)
    • trait BackendCompilationUtilities
    • chisel3.util.MuxLookup(key, default, mapping) (use chisel3.util.MuxLookup(key, default)(mapping), it has much better type inferencing behavior)
  • Clean up Bindings deprecations (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3736)
    • Make already deprecated APIs package private
    • Add deprecation warnings to a few that we missed

Performance

  • Share the globalNamespace in the DynamicContext used for Definition. (by @mikeurbach in https://github.com/chipsalliance/chisel/pull/3700)
    When creating large numbers of Definitions, copying the globalNamespace back and forth becomes a performance bottleneck.

Fixes

Documentation

Dependency Updates

  • Bump firtool-resolver to 1.1.0 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3696)
    The logic for
    • If FIRTOOL_PATH is set, the --version regex failing no longer will return fail, instead it will set version to <unknown>.
    • If FIRTOOL_PATH is set and something fails (firtool not found or cannot execute the binary), then the error will be returned rather than firtool-resolver falling back to fetching the default version.
    • Errors from running firtool will be logged and returned rather than unconditionally turned into "Firtool binary not on FIRTOOL_PATH".
  • Bump firtool resolver to 1.2.0 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3702)
    Now it will fetch llvm-firtool with classifier for the current system rather than the full artifact which contains binaries for all platforms.
  • Bump firtool-resolver to 1.3.0 (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3719)
    To override which firtool is used by Chisel, users can set environment variable CHISEL_FIRTOOL_PATH.
  • [cd] Bump CIRCT from firtool-1.61.0 to firtool-1.62.0 (by @chiselbot in https://github.com/chipsalliance/chisel/pull/3725)

Build and Internal Changes

  • Exclude docs project from Unidoc

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-RC1...v6.0.0-RC2

chisel - Chisel v6.0.0-RC1

Published by jackkoenig 10 months ago

Features

API Modification

Backend Code Generation

Fixes

  • For ModuleTargets, use the OMInstanceTarget target type, like for InstanceTargets
  • Add a new API to request "member" target types
  • set sample_element's probeInfo for Vecs (by @debs-sifive in https://github.com/chipsalliance/chisel/pull/3611)
    For Vecs, also set the probeInfo of their sample_element, which is used to determine its element type.
  • Add type ascription to implicits from instantiable (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3615)
    This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.
  • Enable checkConnect for Property types in MonoConnect. (by @mikeurbach in https://github.com/chipsalliance/chisel/pull/3635)
    Property types never actually called the helper that was factored out of MonoConnect specifically for them. Upon adding this, it turned out that they never had assignCompatDir called either, and this was leaving directions unspecified in aggregates. Both of these have probably lingered since Property types were made subclasses of Data again. This addresses both omissions, leading to earlier error checking for Property type connections.

Documentation

Dependency Updates

Build and Internal Changes

Uncategorized

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M3...v6.0.0-RC1

chisel - Chisel v5.1.0

Published by jackkoenig 11 months ago

Features

  • Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3336)
    • Chisel will now detect when it should print warnings, errors, and deprecations in color.
    • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
    • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
  • Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (backport #3349) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3351)
  • Add support for zero-width bit extraction (backport #3352) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3354)
  • Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3362)
    This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
  • SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3380)
    SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
  • Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3391)
  • SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3405)
    Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
  • Add support for configurable warnings (backport #3414) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3431)
    Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
  • Enrich ShiftRegister with SyncReadMem-based implementation. (backport #2891) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3571)
    Supplement ShiftRegister with SyncReadMem-based implementation.
  • Add --dump-fir option to ChiselStage (backport #3453) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3456)
    This option will dump the .fir before invoking firtool.
    • Additional changes:
      • Use os.lib for invoking firtool
      • Use lazy serialization to avoid holding the entire FIRRTL in memory.
      • Mix NoStackTrace into FirtoolNotFound
      • Fix detection of no firtool

API Deprecation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0...v5.1.0

chisel - Chisel v6.0.0-M3

Published by jackkoenig about 1 year ago

Features

  • Additional changes:
    • Use os.lib for invoking firtool
    • Use lazy serialization to avoid holding the entire FIRRTL in memory.
    • Mix NoStackTrace into FirtoolNotFound
    • Fix detection of no firtool
  • Module.clockOption and Module.resetOption return Option[Clock] and Option[Reset]
  • Add Boolean Property type (by @adkian-sifive in https://github.com/chipsalliance/chisel/pull/3503)
    API Modification: Add Boolean support to Property API
  • Implement CIRCT converter (by @SpriteOvO in https://github.com/chipsalliance/chisel/pull/3466)
  • Add Disable, a new API for disabling simulation constructs (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3497)
    Disable is a new type that represents the concept of disabling a simulation construct. It is handled similarly to the implicit clock and reset except Disable is notionally a function of the current implicit reset. Its default value is "not has been reset", a two-state simulation-only construct that is 0 when simulation starts and only becomes 1 after reset has been asserted, and then de-asserted. Because Disable has simulation-only semantics, it is not a Data and can only be used by simulation-only APIs.

API Modification

API Deprecation

  • Deprecate calling .viewAs on non-hardware (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/3395)
    Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.
  • Deprecate old BoringUtils API (by @jared-barocsi in https://github.com/chipsalliance/chisel/pull/3428)
    BoringUtils.bore(source, sinks), BoringUtils.addSource and BoringUtils.addSink are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source), BoringUtils.tap(source) ...

Backend Code Generation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M2...v6.0.0-M3

chisel - Chisel v6.0.0-M2

Published by jackkoenig over 1 year ago

Features

API Modification

API Deprecation

Backend Code Generation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v6.0.0-M1...v6.0.0-M2

chisel - Chisel v5.0.0

Published by jackkoenig over 1 year ago

Features

  • Ensure that errors in DataView show the problematic fields in a deterministic order.

API Modification

API Deprecation

Performance

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/a005498...v5.0.0

chisel - Chisel v6.0.0-M1

Published by jackkoenig over 1 year ago

Features

  • Ensure that errors in DataView show the problematic fields in a deterministic order.

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-RC2...v6.0.0-M1

chisel - Chisel v5.0.0-RC2

Published by jackkoenig over 1 year ago

Features

  • Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3214)
    SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
  • Added more Connectable customization functions (backport #3227) (by @mergify[bot] in https://github.com/chipsalliance/chisel/pull/3231)
    • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
    • Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
    • Added .as, a useful function on Connectable when users to upcast the Scala type.
    • Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-RC1...v5.0.0-RC2

chisel - Chisel v5.0.0-RC1

Published by jackkoenig over 1 year ago

Features

API Modification

API Deprecation

Fixes

Documentation

Dependency Updates

Build and Internal Changes

Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-M2...v5.0.0-RC1

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