Chisel: A Modern Hardware Design Language
APACHE-2.0 License
Bot releases are visible (Hide)
Published by jackkoenig over 1 year ago
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie! Also check out the API Docs.
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._
)import firrtl._
)
chisel3.internal
, these should never have been publicFor users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.
Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):
cloneType
is now generated for Record
s, it is an error to implement cloneType
manuallyMultiIOModule
(use Module
).asUInt()
is removed, use .asUInt
)RawModule.getPorts
and chisel3.getModulePorts
stop
with non-zero return codeprintf
, assert
, and assume
) will error if you use a Data
in an s-interpolated String (s"..."
), use cf"..."
instead.The MLIR FIRRTL Compiler is much faster than the Scala FIRRTL Compiler (3-7x). Users should should substantial speedups by switching to using MFC.
In addition, while there have been many performance improvements to Chisel itself included in the 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 22% and 5% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_ids
datastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866
IO(Input(UInt(8.W)))
will now create only a single UInt
object instead of 3Instantiate
API for multiply instantiating moduleschisel3
chisel3.experimental.ChiselEnum
was moved to package chisel3
3.6.0 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0. Please bump to 3.5.6 before attempting to upgrade to 3.6.0.
All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.
For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow: -Wconf:msg=Importing from firrtl:s"
. This will silence the warnings telling you to move off of SFC.
Published by jackkoenig over 1 year ago
chisel3.util.MuxLookup.fromEnum
.fir
. Now emitting FIRRTL version 1.2.0.MuxLookup.apply
that takes two parameter lists instead of one. This helps the scala compiler report better type errors.svsim
, a low level library for simulating SystemVerilog using Verilator and VCS. (by @GeorgeLyon in https://github.com/chipsalliance/chisel/pull/3121)svsim
, a new library for compiling and controlling SystemVerilog simulations in Scala using Verilator or VCS.Simulator
class for simulating Chisel modules with svsim
(by @GeorgeLyon in https://github.com/chipsalliance/chisel/pull/3136)
chisel3.simulator.Simulator
for simulating Chisel modules with svsim
Chisel
and the NotStrict
compile options.Module
or BlackBox
.gcc
versions (by @GeorgeLyon in https://github.com/chipsalliance/chisel/pull/3132)git describe --tag
. SNAPSHOTs will now be unique per push to main.Full Changelog: https://github.com/chipsalliance/chisel/compare/v5.0.0-M1...v5.0.0-M2
Published by jackkoenig over 1 year ago
firrtl
, chisel3-macros
, chisel3-core
, and chisel3
artifacts into a single artifact: chisel
.Full Changelog: https://github.com/chipsalliance/chisel/compare/a005498...v5.0.0-M1
Published by jackkoenig over 1 year ago
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie! Also check out the API Docs.
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._
)import firrtl._
)
chisel3.internal
, these should never have been publicFor users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.
Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):
cloneType
is now generated for Record
s, it is an error to implement cloneType
manuallyMultiIOModule
(use Module
).asUInt()
is removed, use .asUInt
)RawModule.getPorts
and chisel3.getModulePorts
stop
with non-zero return codeprintf
, assert
, and assume
) will error if you use a Data
in an s-interpolated String (s"..."
), use cf"..."
instead.The MLIR FIRRTL Compiler is much faster than the Scala FIRRTL Compiler (3-7x). Users should should substantial speedups by switching to using MFC.
In addition, while there have been many performance improvements to Chisel itself included in the 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 22% and 5% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_ids
datastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866
IO(Input(UInt(8.W)))
will now create only a single UInt
object instead of 3Instantiate
API for multiply instantiating moduleschisel3
chisel3.experimental.ChiselEnum
was moved to package chisel3
3.6.0-RC3 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0-RC3. Please bump to 3.5.6 before attempting to upgrade to 3.6.0-RC3.
All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.
For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow: -Wconf:msg=Importing from firrtl:s,msg=Importing from firrtl:s"
. This will silence the warnings telling you to move off of SFC.
Published by jackkoenig over 1 year ago
Note: These release notes are a work-in-progress
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie! Also check out the API Docs.
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._
)import firrtl._
)
chisel3.internal
, these should never have been publicFor users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.
Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):
cloneType
is now generated for Record
s, it is an error to implement cloneType
manuallyMultiIOModule
(use Module
).asUInt()
is removed, use .asUInt
)RawModule.getPorts
and chisel3.getModulePorts
stop
with non-zero return codeThe MLIR FIRRTL Compiler is much faster than the Scala FIRRTL Compiler. Users should should substantial speedups by switching to using MFC.
In addition, while there have been many performance improvements to Chisel itself included in the 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_ids
datastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866
IO(Input(UInt(8.W)))
will now create only a single UInt
object instead of 3Instantiate
API for multiply instantiating moduleschisel3
chisel3.experimental.ChiselEnum
was moved to package chisel3
3.6.0-RC2 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0-RC2. Please bump to 3.5.6 before attempting to upgrade to 3.6.0-RC2.
All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.
For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow: -Wconf:msg=Importing from firrtl:s,msg=Importing from firrtl:s"
. This will silence the warnings telling you to move off of SFC.
A common issue MacOS users might see is something like:
dyld[47398]: Library not loaded: '/usr/local/opt/zstd/lib/libzstd.1.dylib'
Referenced from: 'firtool'
Reason: tried: '/usr/local/opt/zstd/lib/libzstd.1.dylib' (no such file), '/usr/local/lib/libzstd.1.dylib' (no such file), '/usr/lib/libzstd.1.dylib' (no such file)
The workaround is to install zstd, eg. with Homebrew brew install zstd
.
This was fixed in firtool 1.32.0, although that particular version of firtool should not be used
There is a known bug when using SyncReadMems with size == 1
and write-first read-under-write behavior. This most often happens when using chisel3.util.Queue
with useSyncReadMem == true
(and entries == 1
). See https://github.com/llvm/circt/issues/4734 for more details.
Published by jackkoenig over 1 year ago
Note: These release notes are a work-in-progress
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie! Also check out the API Docs.
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._
)import firrtl._
)
chisel3.internal
, these should never have been publicFor users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.
Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):
cloneType
is now generated for Record
s, it is an error to implement cloneType
manuallyMultiIOModule
(use Module
).asUInt()
is removed, use .asUInt
)RawModule.getPorts
and chisel3.getModulePorts
stop
with non-zero return codeWhile there have been many performance improvements included in the Chisel 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_ids
datastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866
IO(Input(UInt(8.W)))
will now create only a single UInt
object instead of 3Instantiate
API for multiply instantiating moduleschisel3
chisel3.experimental.ChiselEnum
was moved to package chisel3
3.6.0-RC1 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0-RC1. Please bump to 3.5.6 before attempting to upgrade to 3.6.0-RC1.
All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.
For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow: -Wconf:msg=Importing from firrtl:s,msg=Importing from firrtl:s"
. This will silence the warnings telling you to move off of SFC.
A common issue MacOS users might see is something like:
dyld[47398]: Library not loaded: '/usr/local/opt/zstd/lib/libzstd.1.dylib'
Referenced from: 'firtool'
Reason: tried: '/usr/local/opt/zstd/lib/libzstd.1.dylib' (no such file), '/usr/local/lib/libzstd.1.dylib' (no such file), '/usr/lib/libzstd.1.dylib' (no such file)
The workaround is to install zstd, eg. with Homebrew brew install zstd
.
This is true at least as of firtool 1.31.0 but will hopefully be fixed in a future firtool release.
Published by jackkoenig almost 2 years ago
util.exprimental.decode.bitset
(#2882)Published by jackkoenig almost 2 years ago
Note: These release notes are a work-in-progress
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie!
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._
)Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):
MultiIOModule
(use Module
).asUInt()
is removed, use .asUInt
)RawModule.getPorts
and chisel3.getModulePorts
stop
with non-zero return codeWhile there have been many performance improvements included in the Chisel 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_ids
datastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866
IO(Input(UInt(8.W)))
will now create only a single UInt
object instead of 33.6.0-M2 includes everything from 3.5.5 and before. Some features are newly deprecated in 3.5.5 that are removed in 3.6.0-M2. Please bump to 3.5.5 before attempting to upgrade to 3.6.0-M2.
util.exprimental.decode.bitset
(#2882)For complete changes since 3.6.0-M1, run
git log --oneline $(git merge-base origin/master v3.6.0-M1)..$(git merge-base origin/master v3.6.0-M2)
Published by jackkoenig almost 2 years ago
Note: These release notes are a work-in-progress
The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.
Try it out using this Scastie!
Note that many more deprecations are coming before the release of 3.6.0.
import Chisel._
)While there have been many performance improvements included in the Chisel 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.
_ids
datastructure to reduce its size: https://github.com/chipsalliance/chisel3/pull/2866
IO(Input(UInt(8.W)))
will now create only a single UInt
object instead of 33.6.0-M1 includes everything from 3.5.5 and before. Some features are newly deprecated in 3.5.5 that are removed in 3.6.0-M1. Please bump to 3.5.5 before attempting to upgrade to 3.6.0-M1.
Published by jackkoenig almost 2 years ago
chisel3.experimental.AutoCloneType
and mix it in to their Records
. Chisel will now print a warning when users implement cloneType
themselves. It will be an error to implement cloneType
yourself in Chisel 3.6.Data
equality (===) via extension method (#2669)Published by jackkoenig about 2 years ago
cf
(#2528)Published by jackkoenig over 2 years ago
Published by jackkoenig over 2 years ago
Published by jackkoenig over 2 years ago
Bundle.elements
when -P:chiselplugin:genBundleElements
is passed to Scalac (in SBT this is scalacOptions += "-P:chiselplugin:genBundleElements"
). This results in a ~20-30% speedup for Chisel elaboration (excluding FIRRTL). This feature is disabled by default because it is a breaking change to implement elements for any non-final Bundle (a child class extending the given Bundle will rely on the old elementation via inheritance but will now call the newly implemented one in the superclass instead). Users who intend to publish libraries should not enable the feature until updating to Chisel 3.6. Everyone else should use it beginning in Chisel 3.5.1.val mem0 = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
// This will warn because myClock differs from the implicit clock in scope ("clock")
val port0 = mem0(addr)
withClock(myClock) {
val mem1 = SyncReadMem(4, UInt(8.W))
// This will NOT warn because the clock is the same
val port1 = mem1(addr)
}
val mem2 = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
// This will NOT warn because we pass the clock explicitly at the point of port creation
val port2 = mem2(addr, otherClock)
Published by jackkoenig almost 3 years ago
Please see the porting guide for upgrading from Chisel 3.4.[1]
Chisel is built on top of FIRRTL so some FIRRTL changes can affect Chisel users, please see the FIRRTL v1.5.0 release notes as well.
Data
. Often, this is useful for viewing one subtype of Data
, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. It enables some very powerful design patterns. Please see the documentation and cookbook for more information. (#1955)Bundles
as if they were an instance of a parent type. It solves a longstanding issue with bulk connecting Bundles
when there is an inheritance relationship between them [#661]. See the DataView cookbook for more details.BundleLiterals
for creating literal Vecs. Please see the associated documentation for more details. (#1834)import chisel3.experimental.conversions._
. See the related section of the DataView explanation for more details. (#2277)isOneOf
method to ChiselEnum
(#1966).toBools
(#2170)import Chisel._
. (#2023)?
(#2113)verilog
modifier code blocks so that there is always a newline between code blocks and following material. (#2016)-e
option work with ChiselStage methods (#1630)[1] You can contribute to the porting doc by opening PRs against https://github.com/chipsalliance/chisel3/blob/master/docs/src/appendix/upgrading-from-chisel-3-4.md
Published by jackkoenig almost 3 years ago
Please see the porting guide for upgrading from Chisel 3.4.[1]
3.5.0-RC2 includes all changes from 3.5.0-RC1 so please see the RC1 release notes.
Chisel is built on top of FIRRTL so some FIRRTL changes can affect Chisel users, please see the FIRRTL 1.5.0-RC2 release notes as well.
@instantiable
(#2206)@public
on unimplemented vals (#2182).toBools
(#2170)[1] You can contribute to the porting doc by opening PRs against https://github.com/chipsalliance/chisel3/blob/master/docs/src/appendix/upgrading-from-chisel-3-4.md
Published by chick about 3 years ago
Data
. Often, this is useful for viewing one subtype of Data
, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. (#1955)isOneOf
method to ChiselEnum
(#1966)import Chisel._
. (#2023)?
(#2113)verilog
modifier code blocks so that there is always a newline between code blocks and following material. (#2016)-e
option work with ChiselStage methods (#1630)Published by jackkoenig over 3 years ago
-P:chiselplugin:useBundlePlugin
as a scalacOption. This feature is disabled by default because it is a breaking change to implement cloneType for any non-final Bundle (a child class extending the given Bundle could rely on reflective autoclonetype but will now call the newly implemented one in the superclass instead). Users who intend to publish libraries should not enable the feature until updating to Chisel 3.5. Everyone else should use it beginning in Chisel 3.4.3.Published by chick over 3 years ago
toTarget
fail if called on a Literal (or would otherwise not serialize properly) (#1714) (#1721)Published by chick almost 4 years ago
chisel3
to improve the pointing of reported errors (#1621)-e
option work properly (#1630) (#1631).transform
as the correct API for ChiselStage
(#1651)