Chisel: A Modern Hardware Design Language
APACHE-2.0 License
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This version bumps the firrtl dependency to 1.1.4 and adds the following features and bug fixes:
This release contains bug fixes and updates the expected FIRRTL version.
This release candidate contains a Style Guide (curtesy of Kevin Townsend) and the following bug fixes:
This release contains the following backward incompatible API changes:
If you are using your own build and execution harness that does not use one of the Driver.execute
family, you may need to explicitly load annotations into memory and then set the annotations field of the optionsManager.firrtlOptions
. For an example, see lines 124-125 of chisel-testers/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala.
This release includes the following bug and typo fixes:
This release includes the following new features:
This release of chisel uses version 1.0.2 of firrtl
RegInit
should be used to create a register with a specified initializer.RegNext
should be used to create a register with a specified next value.log2Up
and log2Down
have been deprecated, users should now use log2Ceil
and log2Floor
. Internal references to these functions have been fixed.. (#528)QueueIO
and ArbiterIO
work proper when given zero entries.Record
. (#531)Vec
creation warns when type given is a literal. (#530)OHToUInt
is given only one argument it always returns that. (#546)ShiftRegister
applies the enable to all registers created. (#370)UInt
-& UInt
now returns an SInt
. (#502)asTypeOf
. (#450)
fromBits
currently untouched but will be chisel3-deprecated if possible as a future PR.cloneSupertype
See. #446
oneHotMux
now checks against inconsistent input types.Mux
now checks that each branch is of equivalent type.Vec
construction using above.cloneTypeWidth
from Data
to Bits
. It used to silently drop the width
parameter when called on any non-Bits, this makes uses of it explicit and always correct, minus the Bool
case.cloneTypeWidth
. The only stragglers are Bits.pad
(which can instead create a new UInt
/etc from scratch) and Reg
(which clears widths behind the scenes for you). Not sure how to address the Reg
case.flatten
, hopefully will remove it eventually using more local operations.This is the first Chisel3 BIG4 SNAPSHOT release to support Scala 2.12.
Unfortunately, behavior we've come to rely on when generating anonymous classes structurally has been deemed a bug in Scala 2.12 ("Inferred types for fields").
This is Chisel3 issue (#606).
The following code:
import Chisel._
class MyModule extends Module {
val io = new Bundle {
val in = UInt(INPUT, width = 8)
val out = UInt(OUTPUT, width = 8)
}
io.out := io.in
}
Results in:
Error:(12, 6) value out is not a member of Chisel.Bundle
io.out := io.in
Error:(12, 16) value in is not a member of Chisel.Bundle
io.out := io.in
NOTE: This seems to be constrained to compatibility mode.
The normal chisel3 wrappers IO()
, Wire()
cause the inferred value to be the structural type of their argument (the behavior we desire).
As stated in Chisel3 issue (#606), the work around is to add:
scalacOptions ++= Seq("-Xsource:2.11")
to your build.sbt file if you're using Chisel3 in compatibility mode with Scala 2.12.